Serial ATA (SATA)
Table 53. SATA Reference Clock Input Requirements (continued)
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Notes
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
Cycle-to-cycle at
ref clock input
t
—
—
100
ps
—
CLK_CJ
CLK_PJ
SD_REF_CLK/ SD_REF_CLK total Peak-to-peak jitter
t
–50
—
+50
ps
2, 3
reference clock jitter, phase jitter
(peak-peak)
at ref clock input
Note:
1
Only 100/125/150 MHz have been tested, othe in between values will not work correctly with the rest of the system.
2
3
-12
In a frequency band from 150 kHz to 15 MHz at BER of 10
.
Total peak to peak Deterministic Jitter "D " should be less than or equal to 50 ps.
J
Figure 45 shows the SATA reference clock timing waveform.
T
H
Ref_CLK
T
L
Figure 45. SATA Reference Clock Timing Waveform
16.2 Transmitter (Tx) Output Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
16.2.1 Gen1i/1.5G Transmitter Specifications
Table 54 provides the DC differential transmitter output DC characteristics for the SATA interface at
Gen1i or 1.5 Gbits/s transmission.
Table 54. Gen1i/1.5G Transmitter (Tx) DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
mV
Notes
Tx differential output voltage
Tx differential pair impedance
Note:
V
400
85
500
100
600
115
1
SATA_TXDIFF
p-p
Z
Ω
—
SATA_TXDIFFIM
1
Terminated by 50 Ω load.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
68
Freescale Semiconductor
FREESCALE [ Freescale ]
