Serial ATA (SATA)
Table 59. Gen 1i/1.5G Receiver AC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
UI
Notes
Deterministic jitter, data-data
250 UI
U
—
—
0.35
1
SATA_TXDJ250UI
p-p
Note:
1
Measured at Tx output pins peak to peak phase variation, random data pattern.
16.3.2 Gen2i/3G Receiver (Rx) Specifications
Table 60 provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 60. Gen2i/3G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
V
Z
275
85
500
100
750
115
mVp-p
1
SATA_RXDIFF
Differential RX input impedance
Ω
—
SATA_RXSEIM
Note:
1
Voltage relative to common of either signal comprising a differential pair.
Table 61 provides the differential receiver output AC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
Table 61. Gen 2i/3G Receiver AC Specifications
Parameter
Channel Speed
Symbol
Min
Typical
Max
Units
Notes
t
—
333.2
—
3.0
333.33
—
—
Gbps
ps
—
—
1
CH_SPEED
Unit Interval
Total jitter
T
335.11
0.46
UI
SATA_TXTJfB/10
U
UI
UI
UI
UI
UI
UI
p-p
p-p
p-p
p-p
p-p
p-p
f
= f
/10
C3dB
BAUD
Total jitter
= f
U
—
—
—
—
—
—
—
—
—
—
0.60
0.65
0.35
0.42
0.35
1
1
1
1
1
SATA_TXTJfB/500
f
/500
/1667
C3dB
BAUD
Total jitter
= f
U
SATA_TXTJfB/1667
f
C3dB
BAUD
Deterministic jitter
= f /10
U
SATA_TXDJfB/10
SATA_TXDJfB/500
U
SATA_TXDJfB/1667
f
C3dB
BAUD
Deterministic jitter
= f /500
U
f
C3dB
BAUD
Deterministic jitter
= f /1667
f
C3dB
BAUD
Note:
1
Measured at Tx output pins peak to peak phase variation, random data pattern.
™
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
71
FREESCALE [ Freescale ]
