Serial ATA (SATA)
Table 57. Gen 2i/3G Transmitter AC Specifications (continued)
Parameter
Total jitter
f
C3dB
= f
BAUD
/1667
Deterministic jitter
f
C3dB
= f
BAUD
/10
Deterministic jitter
f
C3dB
= f
BAUD
/500
Deterministic jitter
f
C3dB
= f
BAUD
/1667
Symbol
U
SATA_TXTJfB/1667
U
SATA_TXDJfB/10
U
SATA_TXDJfB/500
U
SATA_TXDJfB/1667
Min
—
—
—
—
Typical
—
—
—
—
Max
0.55
0.17
0.19
0.35
Units
UI
p-p
UI
p-p
UI
p-p
UI
p-p
Notes
1
1
1
1
Note:
1
Measured at Tx output pins peak to peak phase variation, random data pattern.
16.3
Differential Receiver (Rx) Input Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics.
16.3.1
Gen1i/1.5G Receiver Specifications
provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 58. Gen1i/1.5G Receiver Input DC Specifications
Parameter
Differential input voltage
Differential Rx input impedance
Symbol
V
SATA_RXDIFF
Z
SATA_RXSEIM
Min
240
85
Typical
500
100
Max
600
115
Units
mV
p-p
Ω
Notes
1
—
Note:
1
Voltage relative to common of either signal comprising a differential pair.
provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA
interface.
Table 59. Gen 1i/1.5G Receiver AC Specifications
Parameter
Unit interval
Total jitter, data-data
5 UI
Total jitter, data-data
250 UI
Deterministic jitter, data-data
5 UI
Symbol
T
UI
U
SATA_TXTJ5UI
U
SATA_TXTJ250UI
U
SATA_TXDJ5UI
Min
666.4333
—
—
—
Typical
666.667
—
—
—
Max
670.2333
0.43
0.60
0.25
Units
ps
UI
p-p
UI
p-p
UI
p-p
Notes
—
1
1
1
MPC8377E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
70
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
