RESET Initialization
4.3
Real Time Clock Timing
Table 8. RTC AC Timing Specifications
Parameter/Condition
Symbol
t
RTCH
t
RTCL
Min
2x
t
CCB_CLK
2x
t
CCB_CLK
Typical
—
—
Max
—
—
Unit
ns
ns
Notes
provides the real time clock (RTC) AC timing specifications.
RTC clock high time
RTC clock low time
5
RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8555E.
provides the RESET initialization AC timing specifications.
Table 9. RESET Initialization Timing Specifications
Parameter/Condition
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before HRESET
negation
Input setup time for POR configs (other than PLL config) with
respect to negation of HRESET
Input hold time for POR configs (including PLL config) with
respect to negation of HRESET
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of HRESET
Min
100
512
100
4
2
—
Max
—
—
—
—
—
5
Unit
μs
SYSCLKs
μs
SYSCLKs
SYSCLKs
SYSCLKs
1
1
1
1
Notes
Notes:
1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8555E. See the
MPC8555E
PowerQUICC™ III Integrated Communications Processor Reference Manual
for more details.
provides the PLL and DLL lock times.
Table 10. PLL and DLL Lock Times
Parameter/Condition
PLL lock times
DLL lock times
Min
—
7680
Max
100
122,880
Unit
μs
CCB Clocks
1, 2
Notes
Notes:
1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the
minimum and an 8:1 ratio results in the maximum.
2. The CCB clock is determined by the SYSCLK
×
platform PLL ratio.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
16
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
