Clock Timing
4
4.1
Clock Timing
System Clock Timing
Table 6. SYSCLK AC Timing Specifications
Parameter/Condition
Symbol
f
SYSCLK
t
SYSCLK
t
KH
, t
KL
t
KHK
/t
SYSCLK
—
Min
—
6.0
0.6
40
—
Typical
—
—
1.0
—
—
Max
166
—
1.2
60
+/- 150
Unit
MHz
ns
ns
%
ps
Notes
1
—
2
3
4, 5
provides the system clock (SYSCLK) AC timing specifications for the MPC8555E.
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1.
Caution:
The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation
regardless of the input frequency.
4.2
TSEC Gigabit Reference Clock Timing
provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
MPC8555E.
Table 7. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise time
EC_GTX_CLK125 fall time
EC_GTX_CLK125 duty cycle
GMII, TBI
RGMII, RTBI
Symbol
f
G125
t
G125
t
G125R
t
G125F
t
G125H
/t
G125
45
47
Min
—
—
—
—
Typical
125
8
—
—
—
55
53
Max
—
—
1.0
1.0
Unit
MHz
ns
ns
ns
%
1
1
1, 2
Notes
Notes:
1. Timing is guaranteed by design and characterization.
2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
15
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
