JTAG
11 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8555E.
provides the JTAG AC timing specifications as defined in
through
Table 38. JTAG AC Timing Specifications (Independent of SYSCLK)
1
At recommended operating conditions (see
Parameter
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Boundary-scan data
TMS, TDI
Input hold times:
Boundary-scan data
TMS, TDI
Valid times:
Boundary-scan data
TDO
Output hold times:
Boundary-scan data
TDO
JTAG external clock to output high impedance:
Boundary-scan data
TDO
Symbol
2
f
JTG
t
JTG
t
JTKHKL
t
JTGR
& t
JTGF
t
TRST
t
JTDVKH
t
JTIVKH
t
JTDXKH
t
JTIXKH
t
JTKLDV
t
JTKLOV
t
JTKLDX
t
JTKLOX
t
JTKLDZ
t
JTKLOZ
Min
0
30
15
0
25
4
0
20
25
4
4
—
—
3
3
Max
33.3
—
—
2
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
Notes
3
4
ns
—
—
ns
20
25
ns
—
—
ns
19
9
5, 6
5
5
4
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK
to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
JTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the
t
JTG
clock reference (K) going to the high (H) state or setup time. Also, t
JTDXKH
symbolizes JTAG timing (JT) with respect to
the time data input signals (D) went invalid (X) relative to the t
JTG
clock reference (K) going to the high (H) state. Note that,
in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
TCLK
.
5. Non-JTAG signal output timing with respect to t
TCLK
.
6. Guaranteed by design.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
49
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
