I2C
provides the test access port timing diagram.
JTAG
External Clock
VM
t
JTIVKH
t
JTIXKH
TDI, TMS
t
JTKLOV
t
JTKLOX
TDO
t
JTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Output Data Valid
Input
Data Valid
VM
Figure 35. Test Access Port Timing Diagram
12 I
2
C
This section describes the DC and AC electrical characteristics for the I
2
C interface of the MPC8555E.
12.1
I
2
C DC Electrical Characteristics
Table 39. I
2
C DC Electrical Characteristics
provides the DC electrical characteristics for the I
2
C interface of the MPC8555E.
At recommended operating conditions with OV
DD
of 3.3 V ± 5%.
Parameter
Input high voltage level
Input low voltage level
Low level output voltage
Output fall time from V
IH
(min) to V
IL
(max) with a bus
capacitance from 10 to 400 pF
Pulse width of spikes which must be suppressed by the
input filter
Input current each I/O pin (input voltage is between 0.1
×
OV
DD
and 0.9
×
OV
DD
(max)
Capacitance for each I/O pin
Symbol
V
IH
V
IL
V
OL
t
I2KLKV
t
I2KHKL
I
I
C
I
Min
0.7
×
OV
DD
–0.3
0
20 + 0.1
×
C
B
0
–10
—
Max
OV
DD
+ 0.3
0.3
×
OV
DD
0.2
×
OV
DD
250
50
10
10
Unit
V
V
V
ns
ns
μA
pF
Notes
1
2
3
4
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C
B
= capacitance of one bus line in pF.
3. Refer to the
MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual
for information on the
digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OV
DD
is switched off.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
51
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
