Electrical Characteristics
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— PCI 3.3-V compatible
— Selectable hardware-enforced coherency
— Selectable clock source (SYSCLK or independent PCI_CLK)
Power management
— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O
— Supports power save modes: doze, nap, and sleep
— Employs dynamic power management
— Selectable clock source (sysclk or independent PCI_CLK)
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
— Burstiness feature that permits counting of burst events with a programmable time between
bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE 1149.1-compliant, JTAG boundary scan
783 FC-PBGA package
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Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8555E. The MPC8555E is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
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Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
