Electrical Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic
Input voltage
DDR DRAM signals
DDR DRAM reference
Three-speed Ethernet signals
PCI, local bus, DUART,
SYSCLK, system control and
power management, I
2
C, and
JTAG signals
Die-junction Temperature
Symbol
MV
IN
MV
REF
LV
IN
OV
IN
Recommended Value
GND to GV
DD
GND to GV
DD
GND to LV
DD
GND to OV
DD
Unit
V
V
V
V
T
j
0 to 105
°C
shows the undershoot and overshoot voltages at the interfaces of the MPC8555E.
G/L/OV
DD
+ 20%
G/L/OV
DD
+ 5%
V
IH
G/L/OV
DD
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
of t
SYS1
Note:
1. Note that t
SYS
refers to the clock period associated with the SYSCLK signal.
Figure 2. Overshoot/Undershoot Voltage for GV
DD
/OV
DD
/LV
DD
The MPC8555E core voltage must always be provided at nominal 1.2 V (see
for actual
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in
The input voltage threshold scales with
respect to the associated I/O supply voltage. OV
DD
and LV
DD
based receivers are simple CMOS I/O
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced the externally supplied MV
REF
signal (nominally set to
GV
DD
/2) as is appropriate for the SSTL2 electrical signaling standard.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
11
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
