CPM
Sys clk
t
PIIVKH
PIO inputs
t
PIIXKH
t
PIKHOX
PIO outputs
Figure 29. PIO Signal Diagram
10.3
CPM I2C AC Specification
Table 35. I2C Timing
Characteristic
Expression
f
SCL
f
SCL
t
SDHDL
t
SCLCH
t
SCHCL
t
SCHDL
t
SDLCL
t
SCLDX
t
SDVCH
t
SRISE
t
SFALL
t
SCHDH
All Frequencies
Min
0
BRGCLK/16512
1/(2.2 * f
SCL
)
1/(2.2 * f
SCL
)
1/(2.2 * f
SCL
)
2/(divider * f
SCL
)
3/(divider * f
SCL
)
2/(divider * f
SCL
)
3/(divider * f
SCL
)
-
-
2/(divider * f
SCL
)
Max
F
MAX(1)
BRGCLK/48
-
-
-
-
(2)
-
-
-
1/(10 * f
SCL
)
1/(33 * f
SCL
)
-
Unit
Hz
Hz
s
s
s
s
s
s
s
s
s
s
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
2
Start condition hold time
2
Data hold time
Data setup
2
time
2
SDA/SCL rise time
SDA/SCL fall time
Stop condition setup time
Notes:
1. F
MAX
= BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled
and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576
2. divider = f
SCL
/prescaler.
In master mode: divider=BRGCLK/(f
SCL
*prescaler)=2*(I2BRG[DIV]+3)
In slave mode: divider=BRGCLK/(f
SCL
*prescaler)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
47
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
