CPM
Table 33. CPM Input AC Timing Specifications
1
(continued)
Characteristic
PIO inputs—input hold time
COL width high (FCC)
Symbol
2
t
PIIXKH
t
FCCH
Min
3
1
1.5
Unit
ns
CLK
Notes:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
FIIVKH
symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the valid state (V)
relative to the reference clock t
FCC
(K) going to the high (H) state or setup time. And t
TDIXKH
symbolizes the TDM timing
(TD) with respect to the time the input signals (I) reach the invalid state (X) relative to the reference clock t
FCC
(K) going to
the high (H) state or hold time.
3. PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER inputs
are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as asynchronous.
Table 34. CPM Output AC Timing Specifications
1
Characteristic
FCC outputs—internal clock (NMSI) delay
FCC outputs—external clock (NMSI) delay
SCC/SMC/SPI outputs—internal clock (NMSI) delay
SCC/SMC/SPI outputs—external clock (NMSI) delay
TDM outputs/SI delay
PIO outputs delay
Symbol
2
t
FIKHOX
t
FEKHOX
t
NIKHOX
t
NEKHOX
t
TDKHOX
t
PIKHOX
Min
1
2
0.5
2
2.5
1
Max
5.5
8
10
8
11
11
Unit
ns
ns
ns
ns
ns
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
FIKHOX
symbolizes the FCC
inputs internal timing (FI) for the time t
FCC
memory clock reference (K) goes from the high state (H) until outputs (O) are
invalid (X).
provides the AC test load for the CPM.
Output
Z
0
= 50
Ω
OV
DD
/2
R
L
= 50
Ω
Figure 22. CPM AC Test Load
through
represent the AC timing from
and
Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
44
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
