CPM
SDA
SCL
tSCLCH
tSCHCL
tSDHDL
tSCHDL
tSCLDX
tSDVCH
tSDLCL
tSRISE
tSFALL
tSCHDH
Figure 30. CPM I2C Bus Timing Diagram
The following two tables are examples of I2C AC parameters at I2C clock value of 100k and 400k
respectively.
Table 36. CPM I2C Timing (f
=100KHz)
SCL
Frequency = 100KHz
Characteristic
SCL clock frequency (slave)
Expression
Unit
Min
Max
fSCL
100
KHz
KHz
μs
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
fSCL
-
4.7
4.7
4
100
tSDHDL
tSCLCH
tSCHCL
tSCHDL
tSDLCL
tSCLDX
tSDVCH
tSRISE
tSFALL
tSCHDH
-
-
μs
High period of SCL
-
μs
Start condition setup time
Start condition hold time
Data hold time
2
-
μs
3
-
μs
2
-
μs
Data setup time
3
-
1
μs
SDA/SCL rise time
-
μs
SDA/SCL fall time (master)
Stop condition setup time
-
303
-
ns
2
μs
Table 37. CPM I2C Timing (f
=400KHz)
SCL
Frequency = 400KHz
Characteristic
Expression
Unit
Min
Max
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
fSCL
400
KHz
KHz
μs
μs
μs
ns
fSCL
-
400
tSDHDL
tSCLCH
tSCHCL
tSCHDL
tSDLCL
tSCLDX
tSDVCH
tSRISE
tSFALL
tSCHDH
1.2
1.2
1
-
-
High period of SCL
-
Start condition setup time
Start condition hold time
Data hold time
420
630
420
630
-
-
-
-
ns
ns
Data setup time
-
ns
SDA/SCL rise time
250
75
-
ns
SDA/SCL fall time
-
ns
Stop condition setup time
420
ns
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
48
FREESCALE [ Freescale ]
