RESET Initialization
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 127 MHz.
For 8-bit Encoded FIFO mode:
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/3.2
For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency
should be no more than 167 MHz.
4.6
Other Input Clocks
For information on the input clocks of other functional blocks of the platform such as SerDes and eTSEC,
see the respective sections of this document.
5
RESET Initialization
Table 8. RESET Initialization Timing Specifications
Parameter/Condition
Min
100
3
100
4
2
—
Max
—
—
—
—
—
5
Unit
μs
SYSCLKs
μs
SYSCLKs
SYSCLKs
SYSCLKs
Notes
2
1
—
1
1
1
Table 8
describes the AC electrical specifications for the RESET initialization timing.
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL config input setup time with stable SYSCLK before HRESET
negation
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
Maximum valid-to-high impedance time for actively driven POR configs
with respect to negation of HRESET
Notes:
1. SYSCLK is the primary clock input for the MPC8572E.
2. Reset assertion timing requirements for DDR3 DRAMs may differ.
Table 9
provides the PLL lock times.
Table 9. PLL Lock Times
Parameter/Condition
PLL lock times
Local bus PLL
Symbol
—
—
Min
100
50
Typical
μs
μs
Max
—
—
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
18
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
