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MPC8572EVTARLB 参数 Datasheet PDF下载

MPC8572EVTARLB图片预览
型号: MPC8572EVTARLB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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DDR2 and DDR3 SDRAM Controller
Table 11. DDR3 SDRAM Interface DC Electrical Characteristics for GV
DD
(typ) = 1.5 V (continued)
Parameter/Condition
Output leakage current
Symbol
I
OZ
Min
–50
Typical
50
Max
μA
Unit
3
Notes:
1. GV
DD
is expected to be within 50 mV of the DRAM GV
DD
at all times.
2. MV
REF
n
is expected to be equal to 0.5
×
GV
DD
, and to track GV
DD
DC variations as measured at the receiver.
Peak-to-peak noise on MV
REF
n
may not exceed ±1% of the DC value.
3. Output leakage is measured with all outputs disabled, 0 V
V
OUT
GV
DD
.
Table 12
provides the DDR SDRAM Controller interface capacitance for DDR2 and DDR3.
Table 12. DDR2 and DDR3 SDRAM Interface Capacitance for GV
DD
(typ)=1.8 V and 1.5 V
Parameter/Condition
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Symbol
C
IO
C
DIO
Min
6
Typical
8
0.5
Max
pF
pF
Unit
1, 2
1, 2
Note:
1. This parameter is sampled. GV
DD
= 1.8 V ± 0.090 V (for DDR2), f = 1 MHz, T
A
= 25°C, V
OUT
= GV
DD
/2, V
OUT
(peak-to-peak) = 0.2 V.
2. This parameter is sampled. GV
DD
= 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, T
A
= 25°C, V
OUT
= GV
DD
/2, V
OUT
(peak-to-peak) = 0.175 V.
Table 13
provides the current draw characteristics for MV
REF
n.
Table 13. Current Draw Characteristics for MV
REF
n
Parameter / Condition
Current draw for MV
REF
n
DDR2 SDRAM
DDR3 SDRAM
Symbol
I
MVREF
n
Min
Max
1500
1250
Unit
μA
Note
1
1. The voltage regulator for MV
REF
n
must be able to supply up to 1500
μA
or 1250 uA current for DDR2 or DDR3 respectively.
6.2
DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The
DDR controller supports both DDR2 and DDR3 memories. Note that although the minimum data rate for
most off-the-shelf DDR3 DIMMs available is 800 MHz, JEDEC specification does allow the DDR3 to run
at the data rate as low as 606 MHz. Unless otherwise specified, the AC timing specifications described in
this section for DDR3 is applicable for data rate between 606 MHz and 800 MHz, as long as the DC and
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
20
Freescale Semiconductor