欢迎访问ic37.com |
会员登录 免费注册
发布采购

MPC8572EVTARLB 参数 Datasheet PDF下载

MPC8572EVTARLB图片预览
型号: MPC8572EVTARLB
PDF下载: 下载PDF文件 查看货源
内容描述: MPC8572E的PowerQUICC III集成处理器硬件规格 [MPC8572E PowerQUICC III Integrated Processor Hardware Specifications]
分类和应用: 外围集成电路PC时钟
文件页数/大小: 140 页 / 1412 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
 浏览型号MPC8572EVTARLB的Datasheet PDF文件第15页浏览型号MPC8572EVTARLB的Datasheet PDF文件第16页浏览型号MPC8572EVTARLB的Datasheet PDF文件第17页浏览型号MPC8572EVTARLB的Datasheet PDF文件第18页浏览型号MPC8572EVTARLB的Datasheet PDF文件第20页浏览型号MPC8572EVTARLB的Datasheet PDF文件第21页浏览型号MPC8572EVTARLB的Datasheet PDF文件第22页浏览型号MPC8572EVTARLB的Datasheet PDF文件第23页  
DDR2 and DDR3 SDRAM Controller
6
DDR2 and DDR3 SDRAM Controller
This section describes the DC and AC electrical specifications for the DDR2 and DDR3 SDRAM
controller interface of the MPC8572E. Note that the required GV
DD
(typ) voltage is 1.8Vor 1.5V when
interfacing to DDR2 or DDR3 SDRAM respectively.
6.1
DDR2 and DDR3 SDRAM Interface DC Electrical Characteristics
Table 10
provides the recommended operating conditions for the DDR SDRAM Controller of the
MPC8572E when interfacing to DDR2 SDRAM.
Table 10. DDR2 SDRAM Interface DC Electrical Characteristics for GV
DD
(typ) = 1.8 V
Parameter/Condition
I/O supply voltage
I/O reference voltage
I/O termination voltage
Input high voltage
Input low voltage
Output leakage current
Output high current (V
OUT
= 1.420 V)
Output low current (V
OUT
= 0.280 V)
Symbol
GV
DD
MV
REF
n
V
TT
V
IH
V
IL
I
OZ
I
OH
I
OL
Min
1.71
0.49
×
GV
DD
MV
REF
n
– 0.04
MV
REF
n
+ 0.125
–0.3
–50
–13.4
13.4
Max
1.89
0.51
×
GV
DD
MV
REF
n
+ 0.04
GV
DD
+ 0.3
MV
REF
n
– 0.125
50
Unit
V
V
V
V
V
μA
mA
mA
Notes
1
2
3
4
Notes:
1. GV
DD
is expected to be within 50 mV of the DRAM GV
DD
at all times.
2. MV
REF
n
is expected to be equal to 0.5
×
GV
DD
, and to track GV
DD
DC variations as measured at the receiver.
Peak-to-peak noise on MV
REF
n
may not exceed ±2% of the DC value.
3. V
TT
is not applied directly to the device. It is the supply to that far end signal termination is made and is expected to be
equal to MV
REF
n.
This rail should track variations in the DC level of MV
REF
n.
4. Output leakage is measured with all outputs disabled, 0 V
V
OUT
GV
DD
.
Table 11
provides the recommended operating conditions for the DDR SDRAM Controller of the
MPC8572E when interfacing to DDR3 SDRAM.
Table 11. DDR3 SDRAM Interface DC Electrical Characteristics for GV
DD
(typ) = 1.5 V
Parameter/Condition
I/O supply voltage
I/O reference voltage
Input high voltage
Input low voltage
Symbol
GV
DD
MV
REF
n
V
IH
V
IL
Min
1.425
0.49
×
GV
DD
MV
REF
n
+ 0.100
GND
Typical
1.575
0.51
×
GV
DD
GV
DD
MV
REF
n
– 0.100
Max
V
V
V
V
Unit
1
2
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
19