Ethernet Management Interface Electrical Characteristics
Table 44. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LV
DD
/TV
DD
of 3.3 V ± 5% or 2.5 V ± 5%.
Parameter/Condition
ECn_MDIO to ECn_MDC hold time
ECn_MDC rise time
ECn_MDC fall time
Symbol
1
t
MDDXKH
t
MDCR
t
MDHF
Min
0
—
—
Typ
—
—
—
Max
—
10
10
Unit
ns
ns
ns
Notes
—
4
4
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(first two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
MDKHDX
symbolizes management data timing (MD) for the time t
MDC
from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, t
MDDVKH
symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the t
MDC
clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (f
CCB
). The actual
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8572E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform
Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, f
MDC
= 533/(2*4*8) = 533/64 = 8.3 MHz.
That is, for a system running at a particular platform frequency (f
CCB
), the ECn_MDC output clock frequency can be
programmed between maximum f
MDC
= f
CCB
/64 and minimum f
MDC
= f
CCB
/448. Refer to MPC8572E reference manual’s
MIIMCFG register section for more detail.
3. The maximum ECn_MDC output clock frequency is defined based on the maximum platform frequency for MPC8572E
(600 MHz) divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum platform
frequency for MPC8572E (400 MHz) divided by 448, following the formula described in Note 2 above. The typical
ECn_MDC output clock frequency of 2.5 MHz is shown for reference purpose per IEEE 802.3 specification.
4. Guaranteed by design.
5. t
plb_clk
is the platform (CCB) clock.
Figure 28
shows the MII management AC timing diagram.
t
MDC
ECn_MDC
t
MDCH
ECn_MDIO
(Input)
t
MDDVKH
t
MDDXKH
ECn_MDIO
(Output)
t
MDKHDX
t
MDCF
t
MDCR
Figure 28. MII Management Interface Timing Diagram
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
52
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
