Local Bus Controller (eLBC)
Table 49. Local Bus General Timing Parameters (BV
DD
= 2.5 V DC)—PLL Enabled (continued)
At recommended operating conditions with BV
DD
of 2.5 V ± 5% (continued)
Parameter
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except LAD/LDP and
LALE)
Output hold from local bus clock for LAD/LDP
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
Local bus clock to output high impedance for LAD/LDP
Symbol
1
t
LBKHOV2
t
LBKHOV3
t
LBKHOV4
t
LBKHOX1
t
LBKHOX2
t
LBKHOZ1
t
LBKHOZ2
Min
—
—
—
0.8
0.8
—
—
Max
2.5
2.4
2.4
—
—
2.6
2.6
Unit
ns
ns
ns
ns
ns
ns
ns
Notes
3
3
3
3
3
5
5
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(First two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example,
t
LBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
LBK
clock
reference (K) goes high (H), in this case for clock one(1). Also, t
LBKHOX
symbolizes local bus timing (LB) for the
t
LBK
clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BV
DD
/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock
for PLL bypass mode to 0.4
×
BV
DD
of the signal in question for 2.5-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
6. t
LBOTOT
is a measurement of the minimum time between the negation of LALE and any change in LAD. t
LBOTOT
is programmed with the LBCR[AHD] parameter.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BV
DD
/2.
8. Guaranteed by design.
Table 50
describes the general timing parameters of the local bus interface at BV
DD
= 1.8 V DC
Table 50. Local Bus General Timing Parameters (BV
DD
= 1.8 V DC)—PLL Enabled
DD
of 1.8 V ± 5%
Parameter
Local bus cycle time
Local bus duty cycle
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LALE output negation to high impedance for LAD/LDP
(LATCH hold time)
Symbol
1
t
LBK
t
LBKH/
t
LBK
t
LBKSKEW
t
LBIVKH1
t
LBIVKH2
t
LBIXKH1
t
LBIXKH2
t
LBOTOT
Min
6.67
43
—
2.4
1.9
1.1
1.1
1.2
Max
12
57
150
—
—
—
—
—
Unit
ns
%
ps
ns
ns
ns
ns
ns
Notes
2
—
7, 8
3, 4
3, 4
3, 4
3, 4
6
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
56
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
