GS1559 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
D8
Name
CANC
Timing
Synchronous
with PCLK
Type
Output
Description
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
HD Mode (SD/HD = LOW)
The CANC signal will be HIGH when the device has detected VANC or
HANC data in the chroma video stream and LOW otherwise.
SD Mode (SD/HD = LOW)
For 20-bit demultiplexed data (20bit/10bit = HIGH), the CANC signal will
be HIGH when VANC or HANC data is detected in the chroma video
stream and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will be
HIGH when VANC or HANC data is detected anywhere in the data stream
and LOW otherwise.
E2
E4
TERM1
SD/HD
Analog
Non
Synchronous
Input
Input /
Output
Termination for serial digital input 1. AC couple to EQ_GND.
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The SD/HD signal will be LOW whenever the received serial digital signal
is 1.485Gb/s or 1.485/1.001Gb/s.
The SD/HD signal will be HIGH whenever the received serial digital signal
is 270Mb/s.
Slave Mode (MASTER/SLAVE = LOW)
When set LOW, the device will be configured for the reception of
1.485Gb/s or 1.485/1.001Gb/s signals only and will not lock to any other
serial digital signal.
When set HIGH, the device will be configured for the reception of 270Mb/s
signals only and will not lock to any other serial digital signal.
NOTE: When in slave mode, reset the device after the SD/HD input has
been initially configured, and after each subsequent SD/HD data rate
change.
NOTE: This pin has an internal pull-up resistor of 100K.
E5, F5
E6, F6
F1
CORE_GND
CORE_VDD
CD1
–
–
Non
Synchronous
Power
Power
Input
Ground connection for the digital core logic. Connect to digital GND.
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI1 and DDI1
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
30572 - 4
July 2005
10 of 74
GENNUM [ GENNUM CORPORATION ]
