GS1559 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Name
Timing
Type
Description
Number
H8
H
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data.
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register accessible via the host interface.
Active Line Blanking (H_CONFIG = 0h)
The H signal will be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1h)
The H signal will be HIGH for the entire horizontal blanking period as
indicated by the H bit in the received TRS ID words, and LOW otherwise.
J1
CD2
Non
Input
STATUS SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI2 and DDI2
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
J5
SDO_EN/DIS
Non
Input
CONTROL SIGNAL INPUT
Synchronous
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
J6
SDIN_TDI
Synchronous
with
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
SCLK_TCK
Serial Data In / Test Data Input
Host Mode (JTAG/HOST = LOW)
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the host interface is not being used, tie this pin HIGH.
J7
V
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking.
The V signal will be HIGH for the entire vertical blanking period as
indicated by the V bit in the received TRS signals.
The V signal will be LOW for all lines outside of the vertical blanking
interval.
K1
RSET
Analog
Input
Used to set the serial digital loop-through output signal amplitude. Connect
to CD_VDD through 281Ω +/- 1% for 800mVp-p single-ended output swing.
30572 - 4 July 2005
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