GS1559 Data Sheet
4.4.1 Output Swing
Nominally, the voltage swing of the serial digital loop-through output is 800mV
p-p
single-ended into a 75Ω load. This is set externally by connecting the RSET pin to
CD_VDD through 281Ω.
The loop-through output swing may be decreased by increasing the value of the
RSET resistor. The relationship is approximated by the curve shown in
Alternatively, the serial digital output can drive 800mVp-p into a 50Ω load. Since
the output swing is reduced by a factor of approximately one third when the smaller
load is used, the RSET resistor must be 187Ω to obtain 800mVp-p.
1000
900
800
ΔV
SDO
(mV
p-p
)
700
600
500
400
300
250
300
350
400
450
500
550
600
650
700
750
RSET(Ω)
Figure 4-1: Serial Digital Loop-Through Output Swing
4.4.2 Reclocker Bypass Control
The serial digital loop-through output may be either a buffered version of the serial
digital input signal, or a reclocked version of that signal.
When operating in slave mode, the application layer may choose the reclocked
output by setting RC_BYP to logic HIGH. If RC_BYP is set LOW, the data stream
will bypass the internal reclocker and the serial digital output will be a buffered
version of the input.
When operating in master mode, the device will assert the RC_BYP pin HIGH only
when it has successfully locked to a SMPTE or DVB-ASI input data stream, (see
In this case, the serial digital loop-through output will be
a reclocked version of the input.
30572 - 4
July 2005
29 of 74
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