GS1559 Data Sheet
5.2 Typical Application Circuit (Part B)
+3.3V
GND_VCO
3
2
1
IO_VDD
10n
IO_GND
10n
4
GND
GO1525
VCTR
GND
VCC
8
VCO_VCC
1u
+1.8V
GND_VCO
VCO_VCC
CORE_VDD
GND_VCO
VCO_VCC
10n
4K75 +/- 1%
+3.3V
0
CP_VDD
4K75 +/- 1%
10n
CP_GND
1u
0
GND_VCO
100n
CORE_GND
GND_D
39K2
+1.8V
BUFF_VDD
PD_VDD
10n
PDBUFF_GND
GND_A
CP_VDD
CP_GND
PDBUFF_GND
PD_VDD
BUFF_VDD
LB_CONT
CP_CAP
LF
VCO_VCC
VCO_GND
VCO
VCO
GND_VCO
CP_VDD
CP_GND
PDBUFF_GND
PD_VDD
BUFF_VDD
CORE_GND
CORE_GND
CORE_VDD
CORE_VDD
IO_GND
IO_GND
IO_GND
IO_VDD
IO_VDD
IO_VDD
IO_GND
GND_D
2n2
0
CORE_VDD
10n
IO_VDD
10n
1u
GND_VCO
+1.8V
+3.3V
10n
GND_VCO
CORE_GND
IO_GND
GND_D
GND_D
10n
IO_VDD
10n
1u
+3.3V
GND_D
1u
GND_VCO
5
6
GND
GND
1u
10n
GND_A
7
O/P
NC
B2
B3
C3
C2
C1
B4
B1
A1
A2
A3
A4
A5
CORE_GND F5
CORE_GND E5
CORE_VDD F6
CORE_VDD E6
IO_GND B8
IO_GND F8
IO_GND J8
IO_VDD A8
IO_VDD E8
IO_VDD K8
DATA[19..0]
+1.8V_A
+3.3V
F1
D1
E2
E1
GND_EQ
CD
DDI2
DDI2
4u7
4u7
GND_EQ
GND_D
10n
0
CD1
DDI_1
TERM1
DDI_1
J1 C D 2
G1 DDI_2
10n
H1 DDI_2
H2 TERM2
K1 RSET
G6
F4
G4
J5
B7
D4
K6
C6
G5
E4
D5
C7
H5
J6
H6
H4
RESET_TRST
20bit/10bit
IOPROC_EN/DIS
SDO_EN/DIS
FW_EN/DIS
IPSEL
JTAG/HOST
MASTER/SLAVE
SMPTE_BYPASS
SD/HD
DVB_ASI
RC_BYP
SCLK_TCK
SDIN_TDI
SDOUT_TDO
CS_TMS
A6
B5
B6
C4
C5
D2
D3
D7
E3
GS1559
281 +/-1%
+1.8V_A
RESET_TRST
20bit/10bit
IOPROC_EN/DIS
SDO_EN/DIS
FW_EN/DIS
IPSEL
JTAG/HOST
MASTER/SLAVE
RESET_TRST
20bit/10bit
IOPROC_EN/DIS
SDO_EN/DIS
FW_EN/DIS
IPSEL
JTAG/HOST
MASTER/SLAVE
10n
SDO
SDO
CD_GND
CD_VDD
RESET_TRST
20bit/10bit
IOPROC_EN/DIS
SDO_EN/DIS
FW_EN/DIS
IPSEL
JTAG/HOST
MASTER/SLAVE
SMPTE_BYPASS
SD/HD
DVB_ASI
RC_BYP
SCLK_TCK
SDIN_TDI
SDOUT_TDO
CS_TMS
DOUT19
DOUT18
DOUT17
DOUT16
DOUT15
DOUT14
DOUT13
DOUT12
DOUT11
DOUT10
DOUT9
DOUT8
DOUT7
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
PCLK
DATA_ERROR
LOCKED
YANC
CANC
FIFO_LD
H
V
F
A10
A9
B10
B9
C10
C9
D10
D9
E10
E9
F10
F9
G10
G9
H10
H9
J10
J9
K10
K9
A7
H7
D6
C8
D8
G8
H8
J7
K7
DATA19
DATA18
DATA17
DATA16
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
PCLK
DATA_ERROR
LOCK
YANC
CANC
FIFO_LD
H
V
F
SMPTE_BYPASS
SD/HD
DVB_ASI
RC_BYP
2k2
2k2
2k2
2k2
SMPTE_BYPASS
SD/HD
DVB_ASI
RC_BYP
10n
10n
+1.8V_A
+1.8V_A
PCLK
DATA_ERROR
LOCK
YANC
GND_A
CANC
FIFO_LD
H
NOTE: See Gennum's Reference Design:
"Interfacing the GS1532 to the GS1528 Multi-rate Cable Driver"
V
F
75
PCLK
DATA_ERROR
LOCK
YANC
CANC
FIFO_LD
H
V
F
GND_A
NOTE: SMPTE_BYPASS, SD/HD, DVB_ASI, and RC_BYP
are INPUTS in slave mode (MASTER/SLAVE = LOW), and
are OUTPUTS in master mode (MASTER/SLAVE = HIGH).
To the GS1528A
Cable Driver
SCLK_TCK
SDIN_TDI
SDOUT_TDO
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
CS_TMS
75
75
30572 - 4
July 2005
K3
K4
K5
K2
E7
F2
F3
F7
G2
G3
G7
H3
J2
J3
J4
70 of 74
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