GS1559 Data Sheet
4.13 JTAG
When the JTAG/HOST input pin of the GS1559 is set HIGH, the host interface port
will be configured for JTAG test operation. In this mode, pins H4 to H6 and J6
become TMS, TCK, TDO, and TDI. In addition, the RESET_TRST pin will operate
as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS1559:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other
devices driving the digital I/O pins. If the tests are to be applied only at ATE, this
can be accomplished with tri-state buffers used in conjunction with the
JTAG/HOST input signal. This is shown in
Application HOST
GS1559
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG_HOST
In-circuit ATE probe
Figure 4-14: In-Circuit JTAG
Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST input signal, but some means for tri-stating the host must
exist in order to use the interface at ATE. This is represented in
Application HOST
GS1559
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
Tri-State
In-circuit ATE probe
JTAG_HOST
Figure 4-15: System JTAG
Please contact your Gennum representative to obtain the BSDL model for the GS1559.
30572 - 4
July 2005
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GENNUM [ GENNUM CORPORATION ]
