IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
CONTROLLED TIMING
(1, 5, 8)
t
WC
ADDRESS
t
AS(6)
t
AW
t
WR(3)
t
HZ
(7)
OE
CE
t
WP
(2)
R/
W
t
LZ
t
WZ
(7)
t
OW
(4)
(4)
t
HZ
(7)
DATA
OUT
t
DW
DATA
IN
t
DH
2720 drw 11
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
CONTROLLED TIMING
(1, 5)
t
WC
ADDRESS
t
AW
CE
t
AS(6)
R/
t
EW(2)
t
1.20
(3)
WR
in
W
t
DW
t
DH
2720 drw 12
DATA
IN
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
=V
IL
and R/
W
= V
IL
.
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
)is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output
Test Load (Figure 2).
8. If
OE
is Low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off data to
be placed on the bus for the required t
DW
. If
OE
is High during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified t
WP
.
6.04
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
