LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
ROUT
3-0
are enabled for output. When
OEC is HIGH, COUT
11-0
and ROUT
3-0
are placed in a high-impedance state.
PAUSEA — LF Interface
TM
Pause
When PAUSEA is HIGH, the Filter A
LF Interface
TM
loading sequence is
halted until PAUSEA is returned to a
LOW state. This effectively allows the
user to load coefficients and control
registers at a slower rate than the
master clock (see the LF Interface
TM
section for a full discussion).
PAUSEB — LF Interface
TM
Pause
When PAUSEB is HIGH, the Filter B LF
Interface
TM
loading sequence is halted
until PAUSEB is returned to a LOW
state. This effectively allows the user
to load coefficients and control regis-
ters at a slower rate than the master
clock (see the LF Interface
TM
section for
a full discussion).
Registers on the rising edge of CLK.
When SHENB is HIGH, data can not be
loaded into the Cascade Registers or
shifted through the I/D Registers and
their contents will not be changed.
In Single Filter Mode, SHENB also
enables or disables the loading of data
into the Input (DIN
11-0
), Reverse
Cascade Output (ROUT
11-0
) and Filter
A I/D Registers. It is important to note
that in Single Filter Mode, both
SHENA and SHENB should be
connected together. Both must be
active to enable data loading in Single
Filter Mode. SHENB is latched on the
rising edge of CLK.
RSLA
3-0
— Filter A Round/Select/Limit
Control
RSLA
3-0
determines which of the
sixteen user-programmable Round/
Select/Limit registers (RSL registers)
are used in the Filter A RSL circuitry.
A value of 0 on RSLA
3-0
selects RSL
register 0. A value of 1 selects RSL
register 1 and so on. RSLA
3-0
is
latched on the rising edge of CLK (see
the round, select, and limit sections for
a complete discussion).
RSLB
3-0
— Filter B Round/Select/Limit
Control
RSLB
3-0
determines which of the sixteen
user-programmable RSL registers are
used in the Filter B RSL circuitry. A
value of 0 on RSLB
3-0
selects RSL
register 0. A value of 1 selects RSL
register 1 and so on. RSLB
3-0
is latched
on the rising edge of CLK (see the round,
select, and limit sections for a complete
discussion).
OED — DOUT Output Enable
When OED is LOW, DOUT
15-0
is
enabled for output. When OED is
HIGH, DOUT
15-0
is placed in a high-
impedance state.
OEC — COUT/ROUT Output Enable
When OEC is LOW, COUT
11-0
and
F
IGURE
4. S
INGLE
F
ILTER
M
ODE
12
ROUT
11-0
12
DIN
11-0
I/D
REGISTERS
I/D
REGISTERS
12
RIN
11-0
12
COUT
11-0
FILTER
A
FILTER
B
RSL
CIRCUIT
16
DOUT
15-0
F
IGURE
5. D
UAL
F
ILTER
M
ODE
12
12
DIN
11-0
I/D
REGISTERS
I/D
REGISTERS
RIN
11-0
FILTER
A
FILTER
B
R.S.L.
CIRCUIT
16
DOUT
15-0
R.S.L.
CIRCUIT
16
ROUT
3-0
/ COUT
11-0
Video Imaging Products
2-5
08/16/2000–LDS.3320-N
LOGIC [ LOGIC DEVICES INCORPORATED ]
