LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
F
IGURE
9. S
INGLE
F
ILTER
, M
ATRIX
M
ULTIPLY
T
IMING
S
EQUENCE
1 Data Set with 16 Coefficient Sets
1
CLK
DIN
11-0
RIN
11-0
CAA
7-0
CAB
7-0
TXFRA/ TXFRB
DOUT
15-0
CENA / CENB
SHENA / SHENB
*
**
***
11 Clocks - First Output of First Data/Coefficient Set
16 Clocks - End of First Data/Coefficient Set
26 Clocks - Final Output of First Data/Coefficient Set
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT15
2
3
11*
12
13
14
15
16**
17
26***
DATA SET 0
DATA SET 0
CF
00
CF
01
CF
02
CF
0A
CF
0B
CF
0C
CF
0D
CF
0E
CF
0F
CF
10
28 clock cycles from the first data
input, DIN
15-0
; device latency for the
first result is 11 clock cycles
(11+17 = 28). The result will appear at
the corresponding filter output,
DOUT
15-0
. Subsequently, for both dual
and single filter mode configurations,
the sum of products will continue to
appear every clock cycle thereafter
until the matrix dimension has been
realized. The total pipeline latency for
a complete [8x8][8x1] matrix-vector
operation is 26 clock cycles and the
total pipeline latency for a complete
[16x16][16x1] matrix-vector operation
is 43 clock cycles. Therefore, to process
two square matrices simultaneoulsy, of
size N=8, a total of 73 clock cycles are
all that is required. Similarly, to
process a single square matrix, of size
N=16, a total of 283 clock cycles are
required.
Once again, the timing diagrams (see
Figure 8 and 9) will assume that the
Configuration Registers, the coefficient
sets, and the data values have been
loaded. The corresponding timing
diagram loading sequence for the
coefficient banks and
Configuration/Control registers are
included in the LF3320 data sheets
F
IGURE
10. D
OUBLE
W
IDE
D
ATA
/C
OEFFICIENT
M
ODE
12
DIN
11-0
12
RIN
11-0
I/D
REGISTERS
I/D
REGISTERS
FILTER
A
FILTER
B
SCALE
R.S.L.
CIRCUIT
16
DOUT
15-0
(Figure 11 and Figure 12 respectively).
Further reference to timing diagram
loading sequence for the RSL registers
are also included in the device data
sheet (Figure 15, Figure 14, and Figure
13). The Filter A and Filter B
LF Interface
TM
are used to load data
into the Filter A and Filter B Configura-
tion Registers and coefficient banks.
The Matrix Multiplication Mode is
valid in the Double Wide
Data/Coefficient Mode. However,
there are some special considerations
when this mode is desired. The
LF3320 must be configured for single
filter mode only, for a maximum (8x8)
matrix. The user must disable the
cascaded filter mode, the accumulator
access mode, and the data reversal
(see Table 7).
Double Wide Data/Coefficient Mode
Video Imaging Products
2-8
08/16/2000–LDS.3320-N
LOGIC [ LOGIC DEVICES INCORPORATED ]
