LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
to be configured for A+B (Table 2 and
Table 4); so that condition A+0 is
satisfied. To accomplish this, bit 0 is to
be reset to 0, bit 1 is to be set to 1, and
bit 2 is to be reset to 0. Writing 002H to
Configuration Register 0 (Filter A) and
Configuration Register 2 (Filter B) will
set the corresponding registers to
satisfy the A+0 condition.
The timing diagrams in Figure 8 and 9
will assume that the Configuration
Registers, the coefficient sets, and the
first set of data values (data set) have
been loaded. Loading input data for an
[8x8][8x1] matrix operation requires 9
clock cycles and loading input data for a
[16x16][16x1] matrix operation requires
17 clock cycles. When configured for an
[8x8][8x1] matrix-vector operation, 8
data values are required for loading.
When configured for a [16x16][16x1]
matrix-vector operation, 16 data values
are required for loading. Each data
value is fed through the I/D Registers,
using the corresponding input.
Once the final data value, of the data
set, has been loaded TXFRA/TXFRB
should be brought LOW for one clock
cycle to complete the loading. Once
this occurs, the data set is then bank
loaded into the respective registers
ready to begin the matrix-vector
multiplication operation. The current
data set will not change until
TXFRA/TXFRB is brought LOW
again. To satisfy the matrix equa-
tion (see Figure 7), the current data set
is held for the duration of the required
matrix dimension while cycling
through each coefficient set
(CENA/CENB must be held LOW).
During this time new data values can be
loaded serially, ready for the next
activation of TXFRA/TXFRB. To
insure the correct evaluation of the
matrix-vector multiplication
equation, it is imperative that the
coefficient values are paired with
their corresponding data values.
For the [8x8][8x1] matrix-vector
configuration (dual filter mode), the
first result will appear 19 clock cycles
from the first data input, DIN
15-0
(Filter A) and RIN
15-0
(Filter B); device
latency for the first result is 10 clock
cycles (10+9 = 19).
The result will appear at the corre-
sponding filter output, DOUT
15-0
(Filter A) and ROUT
3-0
/COUT
11-0
(Filter B). For the [16x16][16x1]
matrix-vector configuration (single
filter mode), the first result will appear
mode, [16x16][16x1] matrix-vector
multiplication.
Some functions of the LF3320 must be
disabled when configured for
matrix-vector multiplication. This will
apply to both the single filter mode and
the dual filter mode; these functions
are data reversal and
interleave/decimation. The LF3320
can be cascaded to realize larger
matrices.
Data reversal can be disabled by
setting bit 6, of Configuration Regis-
ter 1 (Filter A) and Configuration
Register 3 (Filter B), both to 1. The
Odd-Tap, interleave mode will need to
be disabled. Writing a 0 to bit 0 of
Configuration Register 1 and Configu-
ration Register 3 will disable the
odd-tap interleave mode for Filter A
and Filter B. When data is not being
interleaved or decimated, the I/D
Register length should be set to a
length of one (Table 3 and Table 5).
Therefore, writing 040H to Configura-
tion Register 1 and 3 will disable the
data reversal and set the correspond-
ing inherent characteristics for the
desired matrix function.
The Filter A ALU and Filter B ALU are
F
IGURE
8. D
UAL
F
ILTER
, M
ATRIX
M
ULTIPLY
T
IMING
S
EQUENCE
Data Set 1 with 8 Coefficient Sets
1
CLK
DIN
11-0
RIN
11-0
CAA
7-0
CAB
7-0
TXFRA/ TXFRB
DOUT
15-0
ROUT
3-0
/COUT
15-0
CENA / CENB
SHENA / SHENB
*
**
***
8 Clocks - End of First Data/Coefficient Set
10 Clocks - First Output of First Data/Coefficient Set
17 Clocks - Final Output of First Data/Coefficient Set
OUT0
OUT1
OUT7
OUT0
OUT1
Data Set 2 with 8 Coefficient Sets
9
10**
11
17***
18
2
3
8*
DATA SET 0
DATA SET 1
CF
00
CF
01
CF
02
CF
07
CF
10
CF
11
CF
12
CF
17
CF
20
CF
21
Video Imaging Products
2-7
08/16/2000–LDS.3320-N
LOGIC [ LOGIC DEVICES INCORPORATED ]
