Microprocessor Supervisory Circuits
MAX691A/MAX693A/MAX800L/MAX800M
Rp*
CE
V
OUT
CE IN
CE OUT
CE
CE
RAM 1
R1
C1*
PFI
V
CC
V
IN
+5V
MAX691A
MAX693A
MAX800L
MAX800M
GND
CE
RAM 2
R3
R2
MAX691A
MAX693A
MAX800L
MAX800M
PFO
CE
CE
RAM 3
TO
μP
CE
RAM 4
CE
5V
PFO
0V
0V
V
TRIP
= 1.25
R1 + R2
R2
GND
*OPTIONAL
V
L
V
TRIP
V
H
V
IN
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMS.
MINIMUM Rp VALUE IS 1kΩ.
ACTIVE-HIGH
CE LINES
FROM LOGIC
V
H
= 1.25/
R2 I I R3
R1 + R2 I I R3
V
L
- 1.25 + 5 - 1.25 = 1.25
R1
R3
R2
Figure 10. Alternate CE Gating
Figure 11. Adding Hysteresis to the Power-Fail Comparator
If using separate power supplies for V
CC
and VBATT,
VBATT must be less than 0.3V above V
CC
when V
CC
is
above the reset threshold. As described in the previ-
ous section, if VBATT exceeds this limit and power is
lost at V
CC
, current flows continuously from VBATT to
V
CC
via the VBATT-to-V
OUT
diode and the V
OUT
-to-V
CC
switch until the circuit is broken (Figure 8).
Using Separate Power Supplies
for VBATT and V
CC
+5V
R1
V
CC
PFI
PFO
Alternate Chip-Enable Gating
Using memory devices with both CE and
CE
inputs
allows the CE loop to be bypassed. To do this, con-
nect
CE
IN to ground, pull up
CE
OUT to V
OUT
, and
–
connect
CE
OUT to the
CE
input of each memory
device (Figure 10). The CE input of each part then
connects directly to the chip-select logic, which does
not have to be gated.
R2
MAX691A
MAX693A
MAX800L
MAX800M
GND
V-
5V
PFO
0V
Adding Hysteresis to the
Power-Fail Comparator
Hysteresis adds a noise margin to the power-fail com-
parator and prevents repeated triggering of
PFO
when
V
IN
is near the power-fail comparator trip point. Figure
11 shows how to add hysteresis to the power-fail com-
5 - 1.25 = 1.25 - V
TRIP
R1
R2
NOTE:
V
TRIP
IS NEGATIVE.
V
TRIP
V-
0V
Figure 12. Monitoring a Negative Voltage
13
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MAXIM [ MAXIM INTEGRATED PRODUCTS ]
