Microprocessor Supervisory Circuits
MAX691A/MAX693A/MAX800L/MAX800M
Table 1. Reset Pulse Width and Watchdog Timeout Selections
OSC SEL
Low
Low
Floating
Floating
OSC IN
External Clock Input
External Capacitor
Low
Floating
Watchdog Timeout Period
Normal
1024 clks
(600/47pF x C)ms
100ms
1.6s
Immediately After Reset
4096 clks
(2.4/47pF x C)sec
1.6s
1.6s
Reset Timeout Period
2048 clks
(1200/47pF x C)ms
200ms
200ms
MAX691A
MAX693A
MAX800L
MAX800M
50kHz
EXTERNAL
CLOCK
8
OSC SEL
8
7
EXTERNAL
OSCILLATOR
OSC SEL
OSC IN
7
OSC IN
INTERNAL OSCILLATOR
1.6s WATCHDOG
N.C.
N.C.
8
OSC SEL
N.C.
INTERNAL OSCILLATOR
100ms WATCHDOG
8
OSC SEL
7
OSC IN
7
OSC IN
In the high-impedance mode, the leakage currents into
this terminal are ±1µA max over temperature. In the
–
low-impedance mode, the impedance of
CE
IN appears
as a 75Ω resistor in series with the load at
CE
OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
–
drive to
CE
IN and the capacitive loading on the Chip-
–
Enable Output (
CE
OUT) (see Chip-Enable Propagation
Delay vs.
CE
OUT Load Capacitance in the
Typical
Operating Characteristics).
The CE propagation delay
–
is production tested from the 50% point of
CE
IN to the
–
50% point of
CE
OUT using a 50Ω driver and 50pF of
load capacitance (Figure 6). For minimum propagation
delay, minimize the capacitive load at
CE
OUT, and
use a low output-impedance driver.
Figure 3. Oscillator Circuits
Chip-Enable Signal Gating
The MAX691A/MAX693A/MAX800L/MAX800M provide
internal gating of chip-enable (CE) signals to prevent
erroneous data from being written to CMOS RAM in the
event of a power failure. During normal operation, the
CE gate is enabled and passes all CE transitions. When
reset is asserted, this path becomes disabled, prevent-
ing erroneous data from corrupting the CMOS RAM. All
–
these parts use a series transmission gate from
CE
IN to
CE
OUT (Figure 4).
The 10ns max CE propagation delay from
CE
IN to
CE
OUT enables the parts to be used with most µPs.
Chip-Enable Output
In the enabled mode, the impedance of
CE
OUT is
equivalent to 75Ω in series with the source driving
CE
IN. In the disabled mode, the 75Ω transmission gate is
off and
CE
OUT is actively pulled to V
OUT
. This source
turns off when the transmission gate is enabled.
– ——— —
— —— –
LOW LINE Output
LOW LINE
is the buffered output of the reset threshold
comparator.
LOW LINE
typically sinks 3.2mA at 0.1V.
For normal operation (V
CC
above the
LOW LINE
thresh-
old),
LOW LINE
is pulled to V
OUT
.
Power-Fail Comparator
The power-fail comparator is an uncommitted comparator
that has no effect on the other functions of the IC.
Common uses include low-battery indication (Figure 7),
and early power-fail warning (see
Typical Operating
Circuit).
Chip-Enable Input
The Chip-Enable Input (CE IN) is high impedance (dis-
abled mode) while RESET and
RESET
are asserted.
During a power-down sequence where V
CC
falls below
–
the reset threshold or a watchdog fault,
CE
IN assumes
a high-impedance state when the voltage at
CE
IN
goes high or 15µs after reset is asserted, whichever
occurs first (Figure 5).
During a power-up sequence,
CE
IN remains high
impedance, regardless of
CE
IN activity, until reset is
deasserted following the reset timeout period.
Power-Fail Input
Power-Fail Input (PFI) is the input to the power-fail com-
parator. It has a guaranteed input leakage of ±25nA
max over temperature. The typical comparator delay is
25µs from V
IL
to V
OL
(power failing), and 60µs from V
IH
to V
OH
(power being restored). If PFI is not used, con-
nect it to ground.
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