1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Mo d e Re g ist e r 3 (MR3)
The mode register 3 (MR3) controls additional functions and features not available in
the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).
This function is controlled via the bits shown in Figure 60. The MR3 is programmed via
the LOAD MODE command and retains the stored information until it is programmed
again or until the device loses power. Reprogramming the MR3 register will not alter the
contents of the memory array, provided it is performed correctly. The MR3 register must
be loaded when all banks are idle and no data bursts are in progress, and the controller
t
t
must wait the specified time MRD and MOD before initiating a subsequent operation.
Fig u re 60: Mo d e Re g ist e r 3 (MR3) De fin it io n
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
16 15 14 13 12 11 10
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
0
Mode register 3 (MR3)
MPR READ Function
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
MPR MPR_RF
0
Mode Register
M2
MPR Enable
M15 M14
M1 M0
2
3
Mode register set (MR0)
Mode register set 1 (MR1)
Mode register set 2 (MR2)
Mode register set 3 (MR3)
0
1
Normal DRAM operations
Dataflow from MPR
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Predefined pattern
Reserved
Reserved
Reserved
Notes: 1. MR3[16 and 13:4] are reserved for future use and must all be programmed to “0.”
2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.
3. Intended to be used for READ synchronization.
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timing
calibration bit sequence. Bit 2 is the master bit that enables or disables access to the
MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic
concept of the multipurpose register is shown in Figure 61 on page 120.
If MR3[2] is a “0,” then the MPR access is disabled, and the DRAM operates in normal
mode. However, if MR3[2] is a “1,” then the DRAM no longer outputs normal read data
but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to “00,” then a
predefined read pattern for system calibration is selected.
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1 (see Table 69
on page 120). Prior to issuing the MRS command, all banks must be in the idle state (all
t
banks are precharged, and RP is met). When the MPR is enabled, any subsequent READ
or RDAP commands are redirected to the multipurpose register. The resulting operation
when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the
MPR is enabled (see Table 70 on page 121). When the MPR is enabled, only READ or
RDAP commands are allowed until a subsequent MRS command is issued with the MPR
disabled (MR3[2] = 0). Power-down mode, self refresh, and any other nonREAD/ RDAP
command is not allowed during MPR enable mode. The RESET function is supported
during MPR enable mode.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
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119
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