1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 61: Mu lt ip u rp o se Re g ist e r (MPR) Blo ck Dia g ra m
Memory core
MR3[2] = 0 (MPR off)
Multipurpose register
predefined data for READs
MR3[2] = 1 (MPR on)
DQ, DM, DQS, DQS#
Notes: 1. A predefined data pattern can be read out of the MPR with an external READ command.
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the
data flow is defined, the MPR contents can be read out continuously with a regular READ or
RDAP command.
Ta b le 69:
MR3[2]
MPR Fu n ct io n a l De scrip t io n o f MR3 Bit s
MR3[1:0]
MPR
MPR READ Fu n ct io n
Fu n ct io n
0
“Don’t Care”
Normal operation, no MPR transaction
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
1
A[1:0]
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2
(see Table 70 on page 121)
MPR Fu n ct io n a l De scrip t io n
The MPR is a 1-bit-wide logical interface via all DQ balls during a READ command. DQ0
on a x4 and a x8 is the prime DQ and outputs the MPR data while the remaining DQ are
driven LOW. Similarly, for the x16, DQ0 (lower byte) and DQ8 (upper byte) are the prime
DQ and output the MPR data while the remaining DQ drive LOW. The MPR readout
supports fixed READ burst and READ burst chop (MRS and OTF via A12/ BC#) with
regular READ latencies and AC timings applicable, provided the DLL is locked as
required.
MPR addressing for a valid MPR read is as follows:
• A[1:0] must be set to “00” as the burst order is fixed per nibble
• A2 selects the burst order:
– BL8, A2 is set to “0,” and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7
• For burst chop 4 cases, the burst order is switched on the nibble base and:
– A2 = 0; burst order = 0, 1, 2, 3
– A2 = 1; burst order = 4, 5, 6, 7
• Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is
assigned to MSB
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
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