MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
USING INTELLIGENT POWER MODULES
2. Half-Bridge Test Circuit and
Switching Time Definitions.
Figure 6.10 shows the stan-
dard half-bridge test circuit and
switching waveforms. Switch-
ing times and FWDi recovery
characteristics are defined as
shown in this figure.
3. Overcurrent and
Short-Circuit Test
I
trip
levels and timing specifica-
tions in short circuit and
overcurrent are defined as
shown in Figure 6.11. By using
a fixed load resistance the sup-
ply voltage, V
CC
, is gradually
increased until OC and SC trip
levels are reached.
Precautions:
A. Before applying any main bus
voltage, V
CC
, the input termi-
nals should be pulled up by re-
sistors to their corresponding
control supply (or SXR) pin,
each input signal should be
kept in OFF state, and the con-
trol supply should be provided.
After this, the specified ON and
OFF level for each input signal
should be applied. The control
supply should also be applied
to the non-operating arm of the
module under test and inputs
of these arms should be kept
to their OFF state.
B. When performing OC and SC
tests the applied voltage, V
CC
,
must be less than V
CC(prot)
and the turn-off surge voltage
spike must not be allowed to
rise above the V
CES
rating of
the device. (These tests must
not be attempted using a
curve tracer.)
Figure 6.10
Half-Bridge Test Circuit and Switching Time Definitions
+
V
D
OFF
SIGNAL
INTEGRATED
GATE
CONTROL
CIRCUIT
+
+
V
D
ON
PULSE
INTEGRATED
GATE
CONTROL
CIRCUIT
V
CE
I
C
V
CC
t
rr
I
rr
90%
I
C
90%
V
CE
10%
t
c (on)
t
c (off)
10%
I
C
I
CIN
t
d (on)
t
r
t
d (off)
t
f
(t
on
= t
d
(
on
) + t
r
)
(t
off
= t
d (off)
+ t
f
)
Figure 6.11
Over-Current and Short-Circuit Test Circuit
R*
V
CC
ON
PULSE
INTEGRATED
GATE
CONTROL
CIRCUIT
+
V
C
I
C
* R IS SIZED TO CAUSE
SC AND OC CONDITIONS
ON
PULSE
INPUT
SIGNAL
SC
OC
I
C
NORMAL
OPERATION
SC
OC
I
C
OVER
CURRENT
t
off
(OC)
SC
OC
I
C
SHORT
CIRCUIT
Sep.1998
MITSUBISHI [ MITSUBISHI ELECTRIC SEMICONDUCTOR ]
