LIST-XL Family
Operational Characteristics
/E
/W
/CM
DQ15-0
DATA OUT
Figure 1: Read Cycle
/E
/W
/CM
DQ15–0
Figure 2: Write Cycle
COMPARAND WRITE
CYCL E
ASSOCIATED DATA
READ CYCLE
STATUS READ
CYCL E
/E
/CM
/W
DQ15–0
/MF, /MM
DATA
DATA
DATA
/MF AND /MM FLAGS UPDATED
Figure 3: Cycle-to-Cycle Timing Example
Cycle Type
Op-Code
on DQ Bus
Control Bus
/E /CM /W
Comments
Notes
Command read
Command write
Command write
Command write
Command write
Command write
Command write
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
Clear power-up anomalies
Target Control register for reset.
Causes Reset.
Target Control register for initial values.
Control register value.
Target Segment Count Control register
Set both Segment counters to write to Segment 1, 2, and 3, and
read from Segment 0.
TCO CT
0000H
TCO CT
8040H
TCO SC
3808H
1
2
Command write SPS M@HM
L
L
L
Set Data reads from Segment 0 of the Highest-Priority match
Table 5: Initialization Routine Example
Notes:
1.
A software reset using a TCO CT followed by 0000H puts the device in a known state. Good programming practice dictates a software reset for
initialization to account for all possible conditions.
2.
A typical LIST-XL control environment: 48 CAM bits, 16 RAM bits; Disable comparison masking; and Enable address increment. See Table 7 for
Control Register bit assignments.
10
Rev. 3.1
MUSIC [ MUSIC SEMICONDUCTORS ]
