Operational Characteristics
LIST-XL Family
Cycle Type
Cmd Write
/E
L
/CM
L
/W
L
I/O Status
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
HIGH-Z
SPS
SPD
TCO
3
3
3
3
3
Operation
Load Instruction decoder
Load Address register
Load Control register
Load Segment Control register
Read Next Free Address register
Read Address register
Read Status Register bits 15–0
Read Status Register bits 31–16
Read Control register
Read Segment Control register
Read Current Persistent Source or Destination
Load Comparand register
Load Mask Register 1
Load Mask Register 2
Write Memory Array at address
Write Memory Array at Next Free address
Write Memory Array at Highest-Priority match
Read Comparand register
Read Mask Register 1
Read Mask Register 2
Read Memory Array at address
Read Memory Array at Highest-Priority match
Deselected
Notes
1
2,3
3
3
3
3
4
5
3
3
3,10
6,9
7,9
7,9
7,9
7,9
7,9
6, 9
8, 9
8, 9
8, 9
7, 8
Cmd Read
L
L
H
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Data Write
L
H
L
Data Read
L
H
H
H
X
X
Table 3: Input/Output Operations
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Default Command Write cycle destination (does not require a TCO instruction).
Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the instruction loaded in the
previous cycle.
Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command Write or Read cycle only.
NFA register can not be loaded this way.
Default Command Read cycle source (does not require a TCO instruction).
Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of Status Register Bits 15–0.
If next cycle is not a Command Read cycle, any subsequent Command Read cycle accesses the Status Register Bits 15–0.
Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations, SPD CR or SPS CR restores
the Comparand register as the destination or source.
Selected by executing a Select Persistent Destination instruction.
Selected by executing a Select Persistent Source instruction.
Access may require multiple 16-bit Read or Write cycles. The Segment Control register controls the selection of the desired 16-bit segment(s) by
establishing the Segment counters’ start and end limits and count values.
A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a persistent source or
destination. The TCO PS instruction also reads back the Device ID.
Control Register Bits CT3 and CT2 set the Address register
to automatically increment or decrement (or not change)
during sequences of Command or Data cycles. The Address
register will change after executing an instruction that
includes M@[AR] or M@aaaH, or after a data access to the
end limit segment (as set in the Segment Control register)
when the persistent source or destination is M@[AR] or
M@aaaH.
Either the Foreground or Background Address register will
be active, depending on which register set has been selected,
Rev. 3.1
and only the active Address register will be written to or read
from.
Next Free Address Register (NF)
The LIST-XL automatically stores the address of the first
empty memory location in the Next Free Address register,
which is then used as a memory address pointer for M@NF
operations. The Next Free Address register, shown in Table
9 on page 16, can be read using a TCO NF instruction. After
a reset, the Next Free Address register is set to zero.
7
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