LIST-XL Family
Operational Characteristics
CAM Status
/RESET Condition
Validity bits at all memory locations
CAM/RAM Partitioning
Comparison Masking
Skip = 0, Empty = 1 (empty)
64 bits CAM, 0 bits RAM
Disabled
Address register auto-increment or auto-decrement
Source and Destination Segment counters count ranges
Address register and Next Free Address register
Page Address and Device Select registers
Control register after reset (including CT15)
Persistent Destination for Command writes
Persistent Source for Command reads
Persistent Source and Destination for Data reads and writes
Configuration Register set
Disabled
00B to 11B; loaded with 00B
Contain all 0s
Contain all 0s (no change on software reset)
Contains 0008H
Instruction decoder
Status register
Comparand register
Foreground
Table 4: Device Control State After Reset
Status Register
Mask Registers (MR1, MR2)
The 32-bit Status register, as shown in Table 10 on page 16,
is the default source for Command Read cycles. Bit 31 is the
internal Full flag, which will go LOW if there are no empty
memorylocations. Bit30istheinternalMultipleMatchflag,
which will go LOW if a Multiple match was detected. Bits
29 and 28 are the Skip and Empty Validity bits, which reflect
the validity of the last memory location read. After a reset,
theSkipandEmptybitswillread11untilareadormovefrom
memory has occurred. The rest of the Status register down to
bit1containstheaddressoftheHighest-Prioritymatch.After
a reset or a no-match condition, the match address bits will
be all 1s. Bit 0 is the internal Match flag, which will go LOW
if a match was found.
The Mask registers can be used in two different ways, either
to mask compares or to mask data writes and moves. Either
mask register can be selected in the Control register to mask
every compare, or selected by instructions to participate in
datawritesormovestoandfromMemory.Ifabitintheselected
mask register is set to a 0, the corresponding bit in the
Comparand register will enter into a masked compare
operation. If a Mask bit is a 1, the corresponding bit in the
Comparand register will not enter into a masked compare
operation. Bits set to 0 in the mask register cause
corresponding bits in the destination register or memory
location to be updated when masking data writes or moves,
whileabitsetto1willpreventthatbitinthedestinationfrom
being changed.
Comparand Register (CR)
EithertheForegroundorBackgroundMR1canbesetactive,
butafterareset,theForegroundMR1isactivebydefault.MR2
incorporatesa sliding mask, where the datacanbereplicated
one bit at a time to the right or left with no wrap-around by
issuing a Shift Right or Shift Left instruction. The right and
left limits are determined by the CAM/RAM partitioning set
in the Control register. For a Shift Right the upper limit bit
is replicated to the next lower bit, while for a Shift Left the
lower limit bit is replicated to the next higher bit.
The 64-bit Comparand register is the default destination for
data writes and reads, using the Segment Control register to
select which 16-bit segment of the Comparand register is to
be loaded or read out. The persistent source and destination
fordatawritesandreadscanbechangedtothemaskregisters
ormemorybySPSandSPDinstructions.Duringanautomatic
orforcedcompare,theComparandregisterissimultaneously
compared against the CAM portion of all memory locations
with the correct validity condition. Automatic compares
alwayscompareagainstvalidmemorylocations,whileforced
compares, using CMP instructions, can compare against
memorylocationstaggedwithanyspecificvaliditycondition.
The Comparand register may be shifted one bit at a time to
therightorleftbyissuingaShiftRightorShiftLeftinstruction,
with the right and left limits for the wrap-around determined
by the CAM/RAM partitioning set in the Control register.
During shift rights, bits shifted off the LSB of the CAM
partition will reappear at the MSB of the CAM partition.
Likewise, bits shifted off the MSB of the CAM partition will
reappear at the LSB during shift lefts.
8
Rev. 3.1
MUSIC [ MUSIC SEMICONDUCTORS ]
