IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
-A
19
ADV/
LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of
CLK, ADV/
LD
low,
CEN
lo w, and true chip enables.
ADV/
LD
is a synchronous input that is used to load the internal registers with new address and control
when it is sampled low at the rising edge of clock with the chip selected. When ADV/
LD
is low with the
chip deselected, any burst in progress is terminated. When ADV/
LD
is sampled high then the internal
burst counter is advanced for any burst that was in progress. The external addresses are ignored when
ADV/
LD
is sampled high.
R/
W
signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the current cycle takes place one clock
cycle later.
R/
W
Read / Write
I
N/A
CEN
Clock Enable
I
LOW Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs, including
clock are ignored and outputs remain unchanged. The effect of
CEN
sampled high on the device
outputs is as if the low to high clock transition did not occur. For normal operation,
CEN
must be
sampled low at rising edge of clock.
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write
cycles (When R/
W
and ADV/
LD
are sampled low) the appropriate byte write signal (
BW
1
-
BW
4
) must be
valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/
W
is sampled high. The appropriate byte(s) of data are written into the device one cycle
later.
BW
1
-
BW
4
can all be tied low if always doing write to the entire 36-bit word.
LOW Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the IDT71T75702/902
(
CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/
LD
low at the rising edge of clock, initiates a
deselect cycle. The ZBT
TM
has a one cycle deselect, i.e., the data bus will tri-state one clock cycle after
deselect is initiated.
HIGH Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has
inverted polarity but otherwise identical to
CE
1
and
CE
2
.
N/A
N/A
This is the clock input to the IDT71T75702/902. Except for
OE
, all timing refe rences for the device are
made with respect to the rising edge of CLK.
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
BW
1
-
BW
4
Individual Byte
Write Enables
I
CE
1
,
CE
2
Chip Enables
I
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Chip Enable
Clock
Data Input/Output
Linear Burst Order
I
I
I/O
I
LBO
LOW Burst ord er selection input. When
LBO
is high the Interleaved burst sequence is selected. When
LBO
is
low the Linear burst sequence is selected.
LBO
is a static input, and it must not change during device
operation.
LOW Asynchronous output enable.
OE
must be low to read data from the IDT71T75702/902. When
OE
is HIGH
the I/O pins are in a high-impedance state.
OE
does not need to be active ly controlled for read and
write cycles. In normal operation,
OE
can be tied low.
N/A
N/A
N/A
N/A
Gives input command for TAP controller; sampled on rising edge of TCK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of
TCK, while test outputs are driven from falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active d epending on the state of
the TAP controller.
OE
Output Enable
I
TMS
TDI
TCK
TDO
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset
(Optional)
I
I
I
O
TRST
I
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG
LOW reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not
used
TRST
can be left floating. This pin has an internal pullup. Only available in BGA package.
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
HIGH IDT71T75702/902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
This pin has an internal pulldown.
N/A
N/A
N/A
2.5V core power supply.
2.5V I/O Supply.
Ground.
5319 tbl 02
ZZ
V
DD
V
DDQ
V
SS
NOTE:
Sleep Mode
Power Supply
Power Supply
Ground
I
N/A
N/A
N/A
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
ROCHESTER [ Rochester Electronics ]
