IDT71T75702, IDT71T75902, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
A
19
A
18
A
8
A
9
Pin Configuration 1M x 18
NC
BW
2
BW
1
CE
2
A
6
A
7
CE
1
CE
2
NC
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Ambient
Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Commercial
-0.5 to +3.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
0 to +70
-55 to +125
-55 to +125
2.0
50
Industrial
-0.5 to +3.6
-0.5 to V
DD
-0.5 to V
DD
+0.5
-0.5 to V
DDQ
+0.5
-40 to +85
-55 to +125
-55 to +125
2.0
50
Unit
V
V
V
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DDQ
V
SS
NC
NC
I/O
8
I/O
9
V
SS
V
DDQ
I/O
10
I/O
11
V
SS
(1)
V
DD
V
DD
(2)
V
SS
I/O
12
I/O
13
V
DDQ
V
SS
I/O
14
I/O
15
I/O
P2
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
NC
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
SS
(1)
V
DD
ZZ
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
5319 drw 02a
V
TERM
(3,6)
V
TERM
(4,6)
V
TERM
(5,6)
T
A
(7)
T
BIAS
T
STG
P
T
I
OUT
o
C
C
C
o
o
W
mA
5319 tbl 06
NOTES:
1. Pins 14 and 66 do not have to be connected directly to V
SS
as long as the
input voltage is < V
IL
.
2. Pin 16 does not have to be connected directly to V
DD
as long as the input voltage
is > V
IH
.
3. Pins 38, 39 and 43 will be pulled internally to V
DD
if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to V
DD
or V
SS
and
pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)
pins38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will
remain disabled from power up.
4. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
,
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
7. During production testing, the case temperature equals T
A
.
A
5
A
4
A
3
A
2
A
1
A
0
NC / TMS
(3)
NC / TDI
(3)
V
SS
V
DD
NC / TDO
(3)
NC / TCK
(3,4)
LBO
A
11
A
12
A
13
A
14
A
15
A
16
A
17
fBGA Capacitance
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
(T
A
= +25°C, f = 1.0MHz)
°
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
5319 tbl 07b
TQFP Capacitance
Symbol
C
IN
C
I/O
Parameter
(1)
(T
A
= +25°C, f = 1.0MHz)
°
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
5
7
Unit
pF
pF
5319 tbl 07
Input Capacitance
I/O Capacitance
BGA Capacitance
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
(T
A
= +25°C, f = 1.0MHz)
°
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
7
7
Unit
pF
pF
5319 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
ROCHESTER [ Rochester Electronics ]
