Si500D
Parameters
Output Symmetry
Rise and Fall Times (20/80%)
3
LVPECL Output Option
(DC coupling, 50
to V
DD
– 2.0 V)
3
Low Power LVPECL Output Option
(AC coupling, 100
Differential
Load)
LVDS Output Option (2.5/3.3 V)
(R
TERM
= 100
diff)
LVDS Output Option (1.8 V)
(R
TERM
= 100
diff)
HCSL Output Option
Condition
V
DIFF
= 0
LVPECL/LVDS
HCSL/Differential SSTL
Differential CMOS, 15 pF, >80 MHz
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
Mid-level
Diff swing
DC termination per pad
V
OH
, sourcing 9 mA
V
OL
, sinking 9 mA
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
From time V
DD
crosses min spec
supply
Min
46 – 13 ns/T
CLK
—
—
—
V
DD
– 1.5
.720
—
.68
1.15
0.25
0.85
0.25
0.35
0.65
45
V
DD
– 0.6
—
V
TT
+ 0.375
—
V
TT
+ 0.48
—
V
TT
+ 0.48
—
—
—
—
—
—
Typ
—
—
—
1.1
—
—
N/A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
0.6
0.7
Max
54 + 13 ns/T
CLK
460
800
1.6
V
DD
– 1.34
.880
—
.95
1.26
0.45
0.96
0.45
0.425
0.82
55
—
0.6
—
V
TT
– 0.375
—
V
TT
– 0.48
—
V
TT
– 0.48
2
250 + 3 x T
CLK
250 + 3 x T
CLK
12 + 3 x T
CLK
2
2
3
1
1.5
Units
%
ps
ps
ns
V
V
PK
V
V
PK
V
V
PK
V
V
PK
V
V
PK
V
V
V
V
V
ms
ns
ns
µs
ms
ps
RMS
ps
RMS
ps
RMS
ps
RMS
CMOS Output Voltage
SSTL-1.8 Output Voltage
4
SSTL-2.5 Output Voltage
4
SSTL-3.3 Output Voltage
5
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver Stopped
Mode
Return From Tri-State Time
Return From Powerdown Time
Non-CMOS
Period Jitter (1-sigma)
CMOS, C
L
= 7 pF
1.0 MHz – min(20 MHz,
0.4 x F
OUT
),non-CMOS
1.0 MHz – min(20 MHz,
0.4 x F
OUT
),CMOS format
—
—
—
—
Integrated Phase Jitter
Notes:
1.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 °C, shock, vibration, and one solder reflow.
2.
Inclusive of 25 °C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 °C, shock, vibration, and one solder reflow.
3.
See “AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators” for further details regarding
output clock termination recommendations.
4.
V
TT
= .5 x V
DD
.
5.
V
TT
= .45 x V
DD
.
2
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
