C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 10.12. EIE2: Extended Interrupt Enable 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
EXVLD
Bit7
-
Bit6
EX7
Bit5
EX6
Bit4
EX5
Bit3
EX4
Bit2
EADC0
Bit1
ET3
Bit0
00000000
SFR Address:
0xE7
Bit7:
EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt.
This bit sets the masking of the XTLVLD interrupt.
0: Disable all XTLVLD interrupts.
1: Enable interrupt requests generated by the XTLVLD flag (OSCXCN.7)
Reserved. Must Write 0. Reads 0.
EX7: Enable External Interrupt 7.
This bit sets the masking of External Interrupt 7.
0: Disable External Interrupt 7.
1: Enable interrupt requests generated by the External Interrupt 7 input pin.
EX6: Enable External Interrupt 6.
This bit sets the masking of External Interrupt 6.
0: Disable External Interrupt 6.
1: Enable interrupt requests generated by the External Interrupt 6 input pin.
EX5: Enable External Interrupt 5.
This bit sets the masking of External Interrupt 5.
0: Disable External Interrupt 5.
1: Enable interrupt requests generated by the External Interrupt 5 input pin.
EX4: Enable External Interrupt 4.
This bit sets the masking of External Interrupt 4.
0: Disable External Interrupt 4.
1: Enable interrupt requests generated by the External Interrupt 4 input pin.
EADC0: Enable ADC0 End of Conversion Interrupt.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt.
1: Enable interrupt requests generated by the ADC0 Conversion Interrupt.
ET3: Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable all Timer 3 interrupts.
1: Enable interrupt requests generated by the TF3 flag (TMR3CN.7)
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Rev. 1.7
82
SILABS [ SILICON LABORATORIES ]
