STK15C88
nvSRAM OPERATION
The STK15C88 is a versatile memory chip that pro-
vides several modes of operation. The STK15C88
can operate as a standard 32K x 8
SRAM
. It has a
32K x 8 nonvolatile element shadow to which the
SRAM
information can be copied, or from which the
SRAM
can be updated in nonvolatile mode.
SOFTWARE NONVOLATILE
STORE
The STK15C88 software
STORE
cycle is initiated by
executing sequential
READ
cycles from six specific
address locations. During the
STORE
cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the
SRAM
data into
nonvolatile memory. Once a
STORE
cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of
READ
s from specific
addresses is used for
STORE
initiation, it is impor-
tant that no other
READ
or
WRITE
accesses inter-
vene in the sequence or the sequence will be
aborted and no
STORE
or
RECALL
will take place.
To initiate the software
STORE
cycle, the following
READ
sequence must be performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate
STORE
cycle
NOISE CONSIDERATIONS
Note that the STK15C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between V
CC
and V
SS
, using leads and traces that are as short as
possible. As with all high-speed
CMOS
ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK15C88 performs a
READ
cycle whenever E
and G are low and W is high. The address specified
on pins A
0-14
determines which of the 32,768 data
bytes will be accessed. When the
READ
is initiated
by an address transition, the outputs will be valid
after a delay of t
AVQV
(
READ
cycle #1). If the
READ
is
initiated by E or G, the outputs will be valid at t
ELQV
or
at t
GLQV
, whichever is later (
READ
cycle #2). The data
outputs will repeatedly respond to address changes
within the t
AVQV
access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
The software sequence must be clocked with E con-
trolled
READ
s.
Once the sixth address in the sequence has been
entered, the
STORE
cycle will commence and the
chip will be disabled. It is important that
READ
cycles
and not
WRITE
cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the t
STORE
cycle time has
been fulfilled, the
SRAM
will again be activated for
READ
and
WRITE
operation.
SRAM WRITE
A
WRITE
cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the
WRITE
cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
0-7
will be writ-
ten into the memory if it is valid t
DVWH
before the end
of a W controlled
WRITE
or t
DVEH
before the end of an
E controlled
WRITE
.
It is recommended that G be kept high during the
entire
WRITE
cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal cir-
cuitry will turn off the output buffers t
WLQZ
after W
goes low.
SOFTWARE NONVOLATILE
RECALL
A software
RECALL
cycle is initiated with a sequence
of
READ
operations in a manner similar to the soft-
ware
STORE
initiation. To initiate the
RECALL
cycle,
the following sequence of
READ
operations must be
performed:
1.
2.
3.
4.
5.
6.
Read address
Read address
Read address
Read address
Read address
Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate
RECALL
cycle
Document Control #ML0016 Rev 2.0
Jan, 2008
8
SIMTEK [ SIMTEK CORPORATION ]
