STK15C88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
PARAMETER
#1, #2
t
ELQV
t
AVAV
t
ELEH
t
AVQV
g
f
,
f
(V
CC
= 5.0V
±
10%)
STK15C88-25
STK15C88-45
UNITS
MIN
MAX
25
25
25
10
5
5
10
0
10
0
25
0
45
0
15
5
5
15
45
45
20
MIN
MAX
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
GLQV
t
AXQX
g
t
ELQX
t
EHQZ
t
GLQX
t
GHQZ
h
e
d
,
e
h
t
HZ
t
t
OHZ
t
PA
t
PS
t
ELICCH
t
EHICCL
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V
IL
and W > V
IH
; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
f, g
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (DATA OUT)
DATA VALID
3
t
AVQV
SRAM READ CYCLE #2: E and G Controlled
f
ADDR ESS
t
E LE H
1
t
EL Q V
2
29
t
EHAX
11
t
EHI CC L
7
t
EHQ Z
E
27
6
t
ELQ X
G
t
AV QV
4
t
G L QV
9
t
GH Q Z
3
8
t
G L Q X
DQ (D ATA OUT)
10
t
ELI CC H
DAT A VAL ID
AC T IVE
I
CC
ST AND BY
Document Control #ML0016 Rev 2.0
Jan, 2008
4
SIMTEK [ SIMTEK CORPORATION ]
