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Figure 1. Watchdog Recovery Clock
133 MHz. This diagram and description are applicable for all
valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state
of internal logic, stopping and holding the REF clock outputs
in the LOW state may require more than one clock cycle to
complete.
P4 Processor SELP4_K7# = 1
Power-down Assertion (P4 Mode)
When PD# is sampled low by two consecutive rising edges of
CPU# clock then all clock outputs except CPU clocks must be
held low on their next high to low transition. CPU clocks must
be held with the CPU clock pin driven high with a value of 2 x
Iref, and CPU# undriven. Note that Figure 1 shows CPU =
Power-down Deassertion (P4 Mode)
The power-up latency needs to less than 3 ms.
P W R D W N #
C P U T 133M H z
C P U T # 133M H z
P C I 33M H z
A G P 66M H z
U S B 48M H z
R E F 14.318M H z
D D R T 133M H z
D D R C 133M H z
S D R A M 133M H z
Figure 2. Power-down Assertion Timing Waveform (in P4 mode)
Rev 1.0,November 21, 2006
Page 10 of 18
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