CY28341-2
Power-down Deassertion (K7 Mode)
When deasserted PD# to HIGH level, all clocks are enabled
and start running on the rising edge of the next full period in
order to guarantee a glitch-free operation, no partial clock
pulses.
<1.5 msec
PW RDW N#
CPU 133MHz
CPU# 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
SDRAM 133MHz
Figure 5. Power-down Deassertion Timing Waveform (in K7 Mode)
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
0.2-0.3mS
Delay
Wait for
VTT_GD#
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
(Note A)
On
Clock Outputs
Clock VCO
On
Off
Figure 6. VTT_PWGD# Timing Diagram (With Advanced PIII Processor SelP4_K7 = 1)[3]
Note:
3. This time diagram shows that VTT_PWRGD# transits to a logic low in the first time at power-up. After the first high-to-low transition of VTT_PWRGD#, device is
not affected, VTT_PWRGD# is ignored.
Rev 1.0,November 21, 2006
Page 12 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
