CY28341-2
<1.5 msec
PW RDW N#
CPU 133MHz
CPU# 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
SDRAM 133MHz
Figure 3. Power-down Deassertion Timing Waveform (in P4 mode)
AMD K7 processor SELP4_K7# = 0
Power-down Assertion (K7 Mode)
When the PD# signal is asserted LOW, all clocks are disabled
to a low level in an orderly fashion prior to removing power
from the part. When PD# is asserted (forced) LOW, the device
transitions to a shutdown (power-down) mode and all power
supplies may then be removed. When PD# is sampled LOW
by two consecutive rising edges of CPU clock, then all affected
clocks are stopped in a LOW state as soon as possible. When
in power-down (and before power is removed), all outputs are
synchronously stopped in a LOW state (see Figure 3 below),
all PLL’s are shut off, and the crystal oscillator is disabled.
When the device is shut down, the I2C function is also
disabled.
PWRDW N#
CPUOD_T 133MHz
CPUCS_T 133MHz
CPUOD_C 133MHz
CPUCS_C 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
REF 14.318MHz
DDRT 133MHz
DDRC 133MHz
SDRAM 133MHz
Figure 4. Power-down Assertion Timing Waveform (in K7 mode)
Rev 1.0,November 21, 2006
Page 11 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
