CY28405-2
Pin Description
Pin No.
Name
Type
Description
1
FS_A/REF_0
I/O, SE
This pin is the FS_A at power-up and VTT_PWRGD# = 0, then it
becomes REF_0 output. (3.3V 14.318-MHz clock output.)
2
4
FS_B/REF_1
XIN
I/O, SE
I
This pin is the FS_B at power-up and VTT_PWRGD# = 0, then it
becomes REF_1 output. (3.3V 14.318-MHz clock output.)
Crystal Connection or External Reference Frequency Input. This
pin has dual functions. It can be used as an external 14.318 MHz
crystal connection or as an external reference frequency input.
5
XOUT
O, SE
Crystal Connection. Connection for an external 14.318 MHz crystal
output.
39, 42,
38, 41,
45, 44
CPUT(0:1),
CPUC(0:1),
CPUT_ITP,
CPUC_ITP
O, DIF
CPU Clock Output. Differential CPU clock outputs, see Table 1 for
frequency configuration.l
36, 35
26, 29, 30
25
SRCT, SRCC
3V66(2:0)
O, DIF
O, SE
O, SE
Differential Serial Reference Clock.
66 MHz Clock Output. 3.3V 66 MHz clock from internal VCO.
3V66_3/VCH
48 or 66 MHz Clock Output. 3.3V selectable through SMBUS to be
66 MHz or 48 MHz. Default is 66 MHz.
7, 8, 9
PCI_F(0:2)
O, SE
O, SE
Free Running PCI Output. 33 MHz clocks divided down from 3V66.
PCI Clock Output. 33 MHz clocks divided down from 3V66.
12, 13, 14, 15, 18, PCI(0:5)
19
22
21
46
USB_48
DOT_48
IREF
O, SE
O, SE
I
Fixed 48 MHz clock output.
Fixed 48 MHz clock output.
Current Reference. A precision resistor is attached to this pin which
is connected to the internal current reference.
20
33
PD#
I, PU
I
3.3V LVTTL input for PowerDown# active low.
VTT_PWRGD#
3.3V LVTTL input is a level sensitive strobe used to latch the
FS[A:E] input (active low).
32
31
48
47
SDATA
SCLK
VDDA
VSSA
VDD
I/O, PU
I, PU
SMBus compatible SDATA.
SMBus compatible SCLOCK.
3.3V power supply for PLL.
Ground for PLL.
PWR
GND
3, 10, 16, 24, 27,
34, 40
PWR
3.3V Power supply for outputs.
6, 11, 17, 23, 28,
37, 43
VSS
GND
Ground for outputs.
Frequency Select Pins (FS_A, FS_B)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A and FS_B inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A and FS_B input values. For all logic levels
of FS_A and FS_B VTT_PWRGD# employs a one-shot
functionality in that once a valid low on VTT_PWRGD# has
been sampled low, all further VTT_PWRGD#, FS_A, and
FS_B transitions will be ignored. Once “Test Clock Mode” has
been invoked, all further FS_B transitions will be ignored and
FS_A will asynchronously select between the Hi-Z and REF/N
mode. Exiting test mode is accomplished by cycling power
with FS_B in a high or low state.
Rev 1.0,November 22, 2006
Page 2 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
