CY28405-2
Table 4. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Acknowledge from master
Bit
....
....
....
....
....
Description
Data Byte (N–1) –8 bits
Bit
47
Acknowledge from slave
Data Byte N –8 bits
Acknowledge from slave
Stop
48:55
56
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
....
....
....
Table 5. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bits
Write = 0
2:8
9
Slave address – 7 bits
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
11:18
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read = 1
29
29
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
30:37
38
39
Byte Configuration Map
Byte 0: Control Register
Bit
7
@Pup
Name
Description
0
1
Reserved
Reserved, set = 0
6
PCIF
PCI
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength
5
4
3
2
1
0
0
0
Reserved
Reserved
Reserved
Reserved
FS_B
Reserved, set = 0
Reserved, set = 0
1
Reserved, set = 1
1
Reserved, set = 1
HW
HW
Power-up latched value of FS_B pin
Power-up latched value of FS_A pin
FS_A
Rev 1.0,November 22, 2006
Page 4 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
