CY28405-3
Byte 4: Control Register
Bit
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
1
@Pup
USB_48
USB_48
PCIF2
PCIF1
PCIF0
PCIF2
PCIF1
PCIF0
Name
Description
USB_48MHz Drive Strength Control
0 = Low Drive Strength, 1 = High Drive Strength
USB_48MHz Output Enable
0 = Disabled, 1 = Enabled
Allow control of PCIF2 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF1 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
Allow control of PCIF0 with assertion of SW PCI_STP
0 = Free Running, 1 = Stopped with SW PCI_STP
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register
Bit
7
6
5
4
3
2
1
0
1
1
0
1
1
1
1
1
@Pup
DOT_48
Reserved
3V66_3/VCH
3V66_3/VCH
Reserved
3V66_2
3V66_1
3V66_0
Name
DOT_48MHz Output Enable
0 = Disabled, 1 = Enabled
Reserved
3V66_3/VCH Frequency Select
0 = 3V66 mode, 1 = VCH (48MHz) mode
3V66_3/VCH Output Enable
0 = Disabled, 1 = Enabled
Reserved, set = 1
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
Description
Byte 6: Control Register
Bit
7
6
5
0
0
0
@Pup
Reserved
Reserved
CPUC0, CPUT0
CPUC1, CPUT1
CPUT_ITP,CPUC_ITP
SRCT, SRCC
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Name
Reserved, set = 0
Reserved, set = 0
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
SRCT/C Frequency Select
0 = 100Mhz, 1 = 200MHz
Spread Spectrum Mode
0 = down (default), 1 = center
Description
4
3
0
0
Rev 1.0, November 22, 2006
Page 6 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
