CY28410-2
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
VTT_PWRGD#
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 5. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PWRGD# = Low
Delay
>0.25mS
Sample
Inputs straps
VDD_A = 2.0V
Wait for <1.8ms
S0
S3
VDD_A = off
Normal
Operation
Enable Outputs
Power Off
VTT_PWRGD# = toggle
Figure 6. Clock Generator Power-up/Run State Diagram
Absolute Maximum Conditions
Parameter
VDD
Description
Core Supply Voltage
Condition
Min.
–0.5
–0.5
Max.
4.6
Unit
V
VDD_A
VIN
Analog Supply Voltage
Input Voltage
4.6
V
Relative to VSS
–0.5 VDD + 0.5 VDC
TS
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Non-functional
Functional
Functional
SSOP
–65
0
150
70
°C
°C
TA
TJ
–
150
°C
ØJC
Dissipation, Junction to Case
(Mil-Spec 883E Method 1012.1)
39.56
°C/W
TSSOP
20.62
45.29
62.26
ØJA
Dissipation, Junction to Ambient
JEDEC (JESD 51)
SSOP
°C/W
V
TSSOP
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model)
Flammability Rating
MIL-STD-883, Method 3015
At 1/8 in.
2000
–
V–0
1
Moisture Sensitivity Level
Rev 1.0,November 20, 2006
Page 10 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
