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CY28410OXC-2T 参数 Datasheet PDF下载

CY28410OXC-2T图片预览
型号: CY28410OXC-2T
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器为英特尔的Grantsdale芯片组 [Clock Generator for Intel Grantsdale Chipset]
分类和应用: 晶体时钟发生器外围集成电路光电二极管
文件页数/大小: 16 页 / 219 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28410OXC-2T的Datasheet PDF文件第7页浏览型号CY28410OXC-2T的Datasheet PDF文件第8页浏览型号CY28410OXC-2T的Datasheet PDF文件第9页浏览型号CY28410OXC-2T的Datasheet PDF文件第10页浏览型号CY28410OXC-2T的Datasheet PDF文件第12页浏览型号CY28410OXC-2T的Datasheet PDF文件第13页浏览型号CY28410OXC-2T的Datasheet PDF文件第14页浏览型号CY28410OXC-2T的Datasheet PDF文件第15页  
CY28410-2  
Absolute Maximum Conditions  
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing  
is NOT required.  
DC Electrical Specifications  
Parameter  
Description  
Condition  
Min.  
Max.  
Unit  
VDD_A,  
3.3V Operating Voltage  
3.3 5%  
3.135  
3.465  
V
VDD_REF,  
VDD_PCI,  
VDD_3V66,  
VDD_48,  
VDD_CPU  
VILI2C  
VIHI2C  
VIL_FS  
VIH_FS  
VILFS_C  
VIMFS_C  
VIH FS_C  
VIL  
Input Low Voltage  
SDATA, SCLK  
SDATA, SCLK  
2.2  
1.0  
V
V
Input High Voltage  
FS_A/FS_B Input Low Voltage  
FS_A/FS_B Input High Voltage  
FS_C Low Range  
VSS – 0.3  
0.7  
0.35  
V
VDD + 0.5  
0.35  
V
0
V
FS_C Mid Range  
0.7  
1.7  
V
FS_C High Range  
2.1  
VDD  
V
Input Low Voltage  
VSS – 0.5  
2.0  
0.8  
V
VIH  
Input High Voltage  
VDD + 0.5  
V
IIL  
Input Low Leakage Current  
Input High Leakage Current  
Output Low Voltage  
except internal pull-up resistors, 0 < VIN < VDD  
except internal pull-down resistors, 0 < VIN < VDD  
IOL = 1 mA  
–5  
PA  
PA  
V
IIH  
5
0.4  
VOL  
VOH  
Output High Voltage  
IOH = –1 mA  
2.4  
V
IOZ  
High-impedance Output Current  
Input Pin Capacitance  
Output Pin Capacitance  
Pin Inductance  
–10  
10  
PA  
pF  
pF  
nH  
V
CIN  
2
5
COUT  
LIN  
3
6
7
VXIH  
Xin High Voltage  
0.7VDD  
VDD  
0.3VDD  
550  
70  
VXIL  
Xin Low Voltage  
0
V
IDD3.3V  
IPD3.3V  
IPD3.3V  
Dynamic Supply Current  
Power-down Supply Current  
Power-down Supply Current  
At max load and freq per Figure 7  
PD asserted, Outputs driven  
PD asserted, Outputs Hi-Z  
mA  
mA  
mA  
2
AC Electrical Specifications  
Parameter  
Description  
Condition  
Min.  
Max.  
Unit  
Crystal  
TDC  
XIN Duty Cycle  
XIN Period  
The device will operate reliably with input  
duty cycles up to 30/70 but the REF clock  
duty cycle will not be within specification  
47.5  
52.5  
%
TPERIOD  
When XIN is driven from an external clock  
source  
69.841  
71.0  
ns  
TR / TF  
TCCJ  
XIN Rise and Fall Times  
XIN Cycle to Cycle Jitter  
Long-term Accuracy  
Measured between 0.3VDD and 0.7VDD  
As an average over 1-Ps duration  
Over 150 ms  
10.0  
500  
300  
ns  
ps  
LACC  
ppm  
CPU at 0.7V  
TDC  
CPUT and CPUC Duty Cycle  
Measured at crossing point VOX  
43  
57  
%
TPERIOD  
100-MHz CPUT and CPUC Period  
Measured at crossing point VOX  
9.997001 10.00300 ns  
Page 11 of 16  
Rev 1.0,November 20, 2006