CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I
2
C CONTROL INTERFACE
SCAS614 – SEPTEMBER 1998
Terminal Functions
TERMINAL
NAME
1Y0–1Y3
2Y0–2Y3
3Y0–3Y3
4Y0–4Y3
5Y0–5Y1
A
OE
SCLOCK
SDATA
GND
NC
VCC
NO.
4, 5, 8, 9
13, 14, 17, 18
31, 32, 35, 36
40, 41, 44, 45
21, 28
11
38
25
24
6, 10, 15, 19, 22, 26,
27, 30, 34, 39, 43
1, 2, 47, 48
3, 7, 12, 16, 20, 23,
29, 33, 37, 42, 46
I/O
O
O
O
O
O
I
I
I
I/O
3.3-V SDRAM byte 0 clock outputs
3.3-V SDRAM byte 1 clock outputs
3.3-V SDRAM byte 2 clock outputs
3.3-V SDRAM byte 3 clock outputs
3.3-V clock outputs provided for feedback control of external phase-locked loops (PLLs)
Clock input
Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-kΩ pullup resistor is internally integrated.
I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally
integrated.
Ground
No internal connection. Reserved for future use.
3.3-V power supply
DESCRIPTION
I2C DEVICE ADDRESS
A7
H
A6
H
A5
L
A4
H
A3
L
A2
L
A1
H
A0 (R/W)
—
I2C BYTE 0-BIT DEFINITION†
BIT
7
6
5
4
3
2
1
0
DEFINITION
2Y3 enable (pin 18)
2Y2 enable (pin 17)
2Y1 enable (pin 14)
2Y0 enable (pin 13)
1Y3 enable (pin 9)
1Y2 enable (pin 8)
1Y1 enable (pin 5)
1Y0 enable (pin 4)
DEFAULT VALUE
H
H
H
H
H
H
H
H
† When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
TI [ TEXAS INSTRUMENTS ]
