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LMK04828BISQX/NOPB 参数 Datasheet PDF下载

LMK04828BISQX/NOPB图片预览
型号: LMK04828BISQX/NOPB
PDF下载: 下载PDF文件 查看货源
内容描述: LMK0482xB超低噪音,符合JESD204B时钟抖动清除器与双回路锁相环 [LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs]
分类和应用: 时钟
文件页数/大小: 101 页 / 2232 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SNAS605 AP – MARCH 2013 – REVISED JUNE 2013
Electrical Characteristics
(continued)
(3.15 V < V
CC
< 3.45 V, -40 °C < T
A
< 85 °C. Typical values at V
CC
= 3.3 V, T
A
= 25 °C, at the Recommended Operating
Conditions and are
not
assured.)
Symbol
Parameter
Conditions
Crystal Oscillator Mode Specifications
F
XTAL
C
IN
f
PD2
Crystal Frequency Range
Input Capacitance of OSCin port
Phase Detector Frequency
(1)
Min
Typ
Max
Units
Fundamental mode crystal
ESR = 200
Ω
(10 to 30 MHz)
ESR = 125
Ω
(30 to 40 MHz)
-40 to +85 °C
10
1
40
MHz
pF
PLL2 Phase Detector and Charge Pump Specifications
155
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 0
I
CPout
SOURCE
PLL2 Charge Pump Source Current
(2)
MHz
100
400
1600
3200
-100
-400
-1600
-3200
1
4
4
10
%
%
%
10
-118
-121
-222.5
-227
dBc/Hz
nA
µA
µA
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 1
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 2
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 3
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 0
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 1
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 2
V
CPout2
=V
CC
/2, PLL2_CP_GAIN = 3
V
CPout2
=V
CC
/2, T
A
= 25 °C
0.5 V < V
CPout2
< V
CC
- 0.5 V
T
A
= 25 °C
I
CPout
SINK
PLL2 Charge Pump Sink Current
(2)
I
CPout2
%MIS
I
CPout2
V
TUNE
I
CPout2
%TEMP
I
CPout2
TRI
PN10kHz
Charge Pump Sink/Source Mismatch
Magnitude of Charge Pump Current
vs. Charge Pump Voltage Variation
Charge Pump Current vs.
Temperature Variation
Charge Pump Leakage
PLL 1/f Noise at 10 kHz offset
Normalized to
1 GHz Output Frequency
(4)
(3)
0.5 V < V
CPout2
< V
CC
- 0.5 V
.
PLL2_CP_GAIN = 400 µA
PLL2_CP_GAIN = 3200 µA
PLL2_CP_GAIN = 400 µA
PLL2_CP_GAIN = 3200 µA
PN1Hz
(1)
(2)
(3)
Normalized Phase Noise Contribution
dBc/Hz
(4)
Assured by characterization. ATE tested at 122.88 MHz.
This parameter is programmable
A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
PLL_flicker
(f), which is dominant close to the carrier. Flicker
noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
PLL_flicker
(10
kHz) - 20log(Fout / 1 GHz), where L
PLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise,
L(f). To measure L
PLL_flicker
(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean
crystal are important to isolating this noise source from the total phase noise, L(f). L
PLL_flicker
(f) can be masked by the reference
oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L
PLL_flicker
(f)
and L
PLL_flat
(f).
A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L
PLL_flat
(f), is defined as:
PN1HZ=L
PLL_flat
(f) - 20log(N) - 10log(f
PDX
). L
PLL_flat
(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz
bandwidth and f
PDX
is the phase detector frequency of the synthesizer. L
PLL_flat
(f) contributes to the total noise, L(f).
Copyright © 2013, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
Product Folder Links :LMK04826B,
13